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+/*
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+ * linux/arch/arm/mach-sa1100/jornada720.c
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+ *
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+ * HP Jornada720 init code
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+ *
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+ * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
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+ * Copyright (C) 2006 Filip Zyzniewski <filip.zyzniewski@tefnet.pl>
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+ * Copyright (C) 2005 Michael Gernoth <michael@gernoth.net>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ */
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+
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+#include <linux/init.h>
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+#include <linux/kernel.h>
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+#include <linux/tty.h>
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+#include <linux/delay.h>
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+#include <linux/platform_data/sa11x0-serial.h>
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+#include <linux/platform_device.h>
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+#include <linux/ioport.h>
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+#include <linux/mtd/mtd.h>
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+#include <linux/mtd/partitions.h>
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+#include <video/s1d13xxxfb.h>
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+
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+#include <asm/hardware/sa1111.h>
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+#include <asm/page.h>
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+#include <asm/mach-types.h>
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+#include <asm/setup.h>
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+#include <asm/mach/arch.h>
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+#include <asm/mach/flash.h>
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+#include <asm/mach/map.h>
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+
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+#include <mach/hardware.h>
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+#include <mach/irqs.h>
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+
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+#include "generic.h"
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+
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+/*
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+ * HP Documentation referred in this file:
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+ * http://www.jlime.com/downloads/development/docs/jornada7xx/jornada720.txt
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+ */
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+
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+/* line 110 of HP's doc */
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+#define TUCR_VAL 0x20000400
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+
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+/* memory space (line 52 of HP's doc) */
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+#define SA1111REGSTART 0x40000000
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+#define SA1111REGLEN 0x00002000
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+#define EPSONREGSTART 0x48000000
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+#define EPSONREGLEN 0x00100000
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+#define EPSONFBSTART 0x48200000
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+/* 512kB framebuffer */
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+#define EPSONFBLEN 512*1024
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+
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+static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] = {
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+ /* line 344 of HP's doc */
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+ {0x0001,0x00}, // Miscellaneous Register
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+ {0x01FC,0x00}, // Display Mode Register
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+ {0x0004,0x00}, // General IO Pins Configuration Register 0
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+ {0x0005,0x00}, // General IO Pins Configuration Register 1
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+ {0x0008,0x00}, // General IO Pins Control Register 0
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+ {0x0009,0x00}, // General IO Pins Control Register 1
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+ {0x0010,0x01}, // Memory Clock Configuration Register
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+ {0x0014,0x11}, // LCD Pixel Clock Configuration Register
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+ {0x0018,0x01}, // CRT/TV Pixel Clock Configuration Register
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+ {0x001C,0x01}, // MediaPlug Clock Configuration Register
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+ {0x001E,0x01}, // CPU To Memory Wait State Select Register
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+ {0x0020,0x00}, // Memory Configuration Register
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+ {0x0021,0x45}, // DRAM Refresh Rate Register
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+ {0x002A,0x01}, // DRAM Timings Control Register 0
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+ {0x002B,0x03}, // DRAM Timings Control Register 1
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+ {0x0030,0x1c}, // Panel Type Register
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+ {0x0031,0x00}, // MOD Rate Register
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邵敏