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+/*
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+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License
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+ * as published by the Free Software Foundation; either version 2
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+ * of the License, or (at your option) any later version.
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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+ * MA 02110-1301, USA.
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+ */
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+
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+#ifndef __ARCH_ARM_MACH_MX3_CRM_REGS_H__
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+#define __ARCH_ARM_MACH_MX3_CRM_REGS_H__
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+
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+#define CKIH_CLK_FREQ 26000000
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+#define CKIH_CLK_FREQ_27MHZ 27000000
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+#define CKIL_CLK_FREQ 32768
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+
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+extern void __iomem *mx3_ccm_base;
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+
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+/* Register addresses */
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+#define MXC_CCM_CCMR 0x00
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+#define MXC_CCM_PDR0 0x04
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+#define MXC_CCM_PDR1 0x08
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+#define MX35_CCM_PDR2 0x0C
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+#define MXC_CCM_RCSR 0x0C
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+#define MX35_CCM_PDR3 0x10
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+#define MXC_CCM_MPCTL 0x10
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+#define MX35_CCM_PDR4 0x14
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+#define MXC_CCM_UPCTL 0x14
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+#define MX35_CCM_RCSR 0x18
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+#define MXC_CCM_SRPCTL 0x18
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+#define MX35_CCM_MPCTL 0x1C
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+#define MXC_CCM_COSR 0x1C
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+#define MX35_CCM_PPCTL 0x20
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+#define MXC_CCM_CGR0 0x20
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+#define MX35_CCM_ACMR 0x24
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+#define MXC_CCM_CGR1 0x24
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+#define MX35_CCM_COSR 0x28
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+#define MXC_CCM_CGR2 0x28
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+#define MX35_CCM_CGR0 0x2C
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+#define MXC_CCM_WIMR 0x2C
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+#define MX35_CCM_CGR1 0x30
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+#define MXC_CCM_LDC 0x30
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+#define MX35_CCM_CGR2 0x34
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+#define MXC_CCM_DCVR0 0x34
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+#define MX35_CCM_CGR3 0x38
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+#define MXC_CCM_DCVR1 0x38
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+#define MXC_CCM_DCVR2 0x3C
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+#define MXC_CCM_DCVR3 0x40
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+#define MXC_CCM_LTR0 0x44
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+#define MXC_CCM_LTR1 0x48
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+#define MXC_CCM_LTR2 0x4C
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+#define MXC_CCM_LTR3 0x50
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+#define MXC_CCM_LTBR0 0x54
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+#define MXC_CCM_LTBR1 0x58
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+#define MXC_CCM_PMCR0 0x5C
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+#define MXC_CCM_PMCR1 0x60
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+#define MXC_CCM_PDR2 0x64
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+
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+/* Register bit definitions */
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+#define MXC_CCM_CCMR_WBEN (1 << 27)
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+#define MXC_CCM_CCMR_CSCS (1 << 25)
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+#define MXC_CCM_CCMR_PERCS (1 << 24)
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+#define MXC_CCM_CCMR_SSI1S_OFFSET 18
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+#define MXC_CCM_CCMR_SSI1S_MASK (0x3 << 18)
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+#define MXC_CCM_CCMR_SSI2S_OFFSET 21
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+#define MXC_CCM_CCMR_SSI2S_MASK (0x3 << 21)
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+#define MXC_CCM_CCMR_LPM_OFFSET 14
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+#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14)
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+#define MXC_CCM_CCMR_LPM_WAIT_MX35 (0x1 << 14)
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+#define MXC_CCM_CCMR_FIRS_OFFSET 11
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+#define MXC_CCM_CCMR_FIRS_MASK (0x3 << 11)
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+#define MXC_CCM_CCMR_UPE (1 << 9)
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+#define MXC_CCM_CCMR_SPE (1 << 8)
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+#define MXC_CCM_CCMR_MDS (1 << 7)
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+#define MXC_CCM_CCMR_SBYCS (1 << 4)
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+#define MXC_CCM_CCMR_MPE (1 << 3)
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+#define MXC_CCM_CCMR_PRCS_OFFSET 1
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+#define MXC_CCM_CCMR_PRCS_MASK (0x3 << 1)
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