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@@ -466,3 +466,135 @@
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/* Define the bits in registers CCGRx */
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/* Define the bits in registers CCGRx */
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#define MXC_CCM_CCGRx_CG_MASK 0x3
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#define MXC_CCM_CCGRx_CG_MASK 0x3
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+#define MXC_CCM_CCGRx_MOD_OFF 0x0
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+#define MXC_CCM_CCGRx_MOD_ON 0x3
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+#define MXC_CCM_CCGRx_MOD_IDLE 0x1
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+
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+#define MXC_CCM_CCGRx_CG15_MASK (0x3 << 30)
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+#define MXC_CCM_CCGRx_CG14_MASK (0x3 << 28)
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+#define MXC_CCM_CCGRx_CG13_MASK (0x3 << 26)
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+#define MXC_CCM_CCGRx_CG12_MASK (0x3 << 24)
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+#define MXC_CCM_CCGRx_CG11_MASK (0x3 << 22)
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+#define MXC_CCM_CCGRx_CG10_MASK (0x3 << 20)
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+#define MXC_CCM_CCGRx_CG9_MASK (0x3 << 18)
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+#define MXC_CCM_CCGRx_CG8_MASK (0x3 << 16)
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+#define MXC_CCM_CCGRx_CG5_MASK (0x3 << 10)
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+#define MXC_CCM_CCGRx_CG4_MASK (0x3 << 8)
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+#define MXC_CCM_CCGRx_CG3_MASK (0x3 << 6)
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+#define MXC_CCM_CCGRx_CG2_MASK (0x3 << 4)
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+#define MXC_CCM_CCGRx_CG1_MASK (0x3 << 2)
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+#define MXC_CCM_CCGRx_CG0_MASK (0x3 << 0)
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+
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+#define MXC_CCM_CCGRx_CG15_OFFSET 30
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+#define MXC_CCM_CCGRx_CG14_OFFSET 28
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+#define MXC_CCM_CCGRx_CG13_OFFSET 26
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+#define MXC_CCM_CCGRx_CG12_OFFSET 24
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+#define MXC_CCM_CCGRx_CG11_OFFSET 22
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+#define MXC_CCM_CCGRx_CG10_OFFSET 20
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+#define MXC_CCM_CCGRx_CG9_OFFSET 18
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+#define MXC_CCM_CCGRx_CG8_OFFSET 16
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+#define MXC_CCM_CCGRx_CG7_OFFSET 14
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+#define MXC_CCM_CCGRx_CG6_OFFSET 12
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+#define MXC_CCM_CCGRx_CG5_OFFSET 10
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+#define MXC_CCM_CCGRx_CG4_OFFSET 8
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+#define MXC_CCM_CCGRx_CG3_OFFSET 6
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+#define MXC_CCM_CCGRx_CG2_OFFSET 4
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+#define MXC_CCM_CCGRx_CG1_OFFSET 2
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+#define MXC_CCM_CCGRx_CG0_OFFSET 0
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+
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+#define MXC_DPTC_LP_BASE (MX51_GPC_BASE + 0x80)
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+#define MXC_DPTC_GP_BASE (MX51_GPC_BASE + 0x100)
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+#define MXC_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180)
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+#define MXC_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0)
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+#define MXC_PGC_IPU_BASE (MX51_GPC_BASE + 0x220)
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+#define MXC_PGC_VPU_BASE (MX51_GPC_BASE + 0x240)
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+#define MXC_PGC_GPU_BASE (MX51_GPC_BASE + 0x260)
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+#define MXC_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280)
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+#define MXC_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0)
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+#define MXC_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0)
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+#define MXC_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0)
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+#define MXC_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0)
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+#define MXC_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300)
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+
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+/* CORTEXA8 platform */
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+#define MXC_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0)
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+#define MXC_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4)
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+#define MXC_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8)
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+#define MXC_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC)
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+#define MXC_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10)
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+#define MXC_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14)
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+#define MXC_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18)
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+#define MXC_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20)
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+#define MXC_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24)
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+
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+/* DVFS CORE */
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+#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00)
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+#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04)
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+#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08)
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+#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C)
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+#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10)
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+#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14)
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+#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18)
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+#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C)
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+#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20)
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+#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24)
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+#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28)
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+#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C)
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+#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30)
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+#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34)
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+#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38)
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+#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C)
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+#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40)
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+
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+/* GPC */
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+#define MXC_GPC_CNTR (MX51_GPC_BASE + 0x0)
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+#define MXC_GPC_PGR (MX51_GPC_BASE + 0x4)
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+#define MXC_GPC_VCR (MX51_GPC_BASE + 0x8)
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+#define MXC_GPC_ALL_PU (MX51_GPC_BASE + 0xC)
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+#define MXC_GPC_NEON (MX51_GPC_BASE + 0x10)
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+#define MXC_GPC_PGR_ARMPG_OFFSET 8
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+#define MXC_GPC_PGR_ARMPG_MASK (3 << 8)
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+
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+/* PGC */
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+#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0)
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+#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC)
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+#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0)
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+#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC)
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+#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0)
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+#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC)
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+
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+#define MXC_PGCR_PCR 1
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+#define MXC_SRPGCR_PCR 1
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+#define MXC_EMPGCR_PCR 1
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+#define MXC_PGSR_PSR 1
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+
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+
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+#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
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+#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
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+
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+/* SRPG */
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+#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0)
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+#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4)
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+#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8)
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+
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+#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0)
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+#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4)
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+#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8)
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+
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+#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0)
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+#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4)
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+#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8)
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+
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+#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0)
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+#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4)
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+#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8)
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+
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+#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0)
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+#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4)
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+#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8)
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+
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+#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0)
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+#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4)
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+#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8)
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+
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+#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
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