|  | @@ -362,3 +362,76 @@
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				|  |  |  /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
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				|  |  |  #define OMAP4430_FORCEUPDATE_SHIFT					1
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				|  |  |  #define OMAP4430_FORCEUPDATE_MASK					(1 << 1)
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				|  |  | +
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				|  |  | +/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
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				|  |  | +#define OMAP4430_FORCEUPDATEWAIT_SHIFT					8
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				|  |  | +#define OMAP4430_FORCEUPDATEWAIT_MASK					(0xffffff << 8)
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				|  |  | +
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				|  |  | +/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */
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				|  |  | +#define OMAP4430_FORCEWKUP_EN_SHIFT					10
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				|  |  | +#define OMAP4430_FORCEWKUP_EN_MASK					(1 << 10)
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				|  |  | +
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				|  |  | +/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */
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				|  |  | +#define OMAP4430_FORCEWKUP_ST_SHIFT					10
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				|  |  | +#define OMAP4430_FORCEWKUP_ST_MASK					(1 << 10)
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				|  |  | +
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				|  |  | +/* Used by REVISION_PRM */
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				|  |  | +#define OMAP4430_FUNC_SHIFT						16
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				|  |  | +#define OMAP4430_FUNC_MASK						(0xfff << 16)
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				|  |  | +
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				|  |  | +/* Used by PM_GFX_PWRSTCTRL */
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				|  |  | +#define OMAP4430_GFX_MEM_ONSTATE_SHIFT					16
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				|  |  | +#define OMAP4430_GFX_MEM_ONSTATE_MASK					(0x3 << 16)
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				|  |  | +
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				|  |  | +/* Used by PM_GFX_PWRSTST */
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				|  |  | +#define OMAP4430_GFX_MEM_STATEST_SHIFT					4
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				|  |  | +#define OMAP4430_GFX_MEM_STATEST_MASK					(0x3 << 4)
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				|  |  | +
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				|  |  | +/* Used by PRM_RSTST */
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				|  |  | +#define OMAP4430_GLOBAL_COLD_RST_SHIFT					0
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				|  |  | +#define OMAP4430_GLOBAL_COLD_RST_MASK					(1 << 0)
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				|  |  | +
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				|  |  | +/* Used by PRM_RSTST */
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				|  |  | +#define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT				1
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				|  |  | +#define OMAP4430_GLOBAL_WARM_SW_RST_MASK				(1 << 1)
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				|  |  | +
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				|  |  | +/* Used by PRM_IO_PMCTRL */
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				|  |  | +#define OMAP4430_GLOBAL_WUEN_SHIFT					16
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				|  |  | +#define OMAP4430_GLOBAL_WUEN_MASK					(1 << 16)
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				|  |  | +
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				|  |  | +/* Used by PRM_VC_CFG_I2C_MODE */
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				|  |  | +#define OMAP4430_HSMCODE_SHIFT						0
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				|  |  | +#define OMAP4430_HSMCODE_MASK						(0x7 << 0)
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				|  |  | +
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				|  |  | +/* Used by PRM_VC_CFG_I2C_MODE */
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				|  |  | +#define OMAP4430_HSMODEEN_SHIFT						3
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				|  |  | +#define OMAP4430_HSMODEEN_MASK						(1 << 3)
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				|  |  | +
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				|  |  | +/* Used by PRM_VC_CFG_I2C_CLK */
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				|  |  | +#define OMAP4430_HSSCLH_SHIFT						16
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				|  |  | +#define OMAP4430_HSSCLH_MASK						(0xff << 16)
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				|  |  | +
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				|  |  | +/* Used by PRM_VC_CFG_I2C_CLK */
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				|  |  | +#define OMAP4430_HSSCLL_SHIFT						24
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				|  |  | +#define OMAP4430_HSSCLL_MASK						(0xff << 24)
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				|  |  | +
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				|  |  | +/* Used by PM_IVAHD_PWRSTCTRL */
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				|  |  | +#define OMAP4430_HWA_MEM_ONSTATE_SHIFT					16
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				|  |  | +#define OMAP4430_HWA_MEM_ONSTATE_MASK					(0x3 << 16)
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				|  |  | +
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				|  |  | +/* Used by PM_IVAHD_PWRSTCTRL */
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				|  |  | +#define OMAP4430_HWA_MEM_RETSTATE_SHIFT					8
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				|  |  | +#define OMAP4430_HWA_MEM_RETSTATE_MASK					(1 << 8)
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				|  |  | +
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				|  |  | +/* Used by PM_IVAHD_PWRSTST */
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				|  |  | +#define OMAP4430_HWA_MEM_STATEST_SHIFT					4
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				|  |  | +#define OMAP4430_HWA_MEM_STATEST_MASK					(0x3 << 4)
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				|  |  | +
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				|  |  | +/* Used by RM_MPU_RSTST */
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				|  |  | +#define OMAP4430_ICECRUSHER_MPU_RST_SHIFT				1
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				|  |  | +#define OMAP4430_ICECRUSHER_MPU_RST_MASK				(1 << 1)
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				|  |  | +
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				|  |  | +/* Used by RM_DUCATI_RSTST */
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				|  |  | +#define OMAP4430_ICECRUSHER_RST1ST_SHIFT				5
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				|  |  | +#define OMAP4430_ICECRUSHER_RST1ST_MASK					(1 << 5)
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				|  |  | +
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