|
@@ -2721,3 +2721,126 @@ static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
|
|
|
};
|
|
|
|
|
|
/* ocp2scp_usb_phy */
|
|
|
+static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
|
|
|
+ .name = "ocp2scp_usb_phy",
|
|
|
+ .class = &omap44xx_ocp2scp_hwmod_class,
|
|
|
+ .clkdm_name = "l3_init_clkdm",
|
|
|
+ .main_clk = "ocp2scp_usb_phy_phy_48m",
|
|
|
+ .prcm = {
|
|
|
+ .omap4 = {
|
|
|
+ .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
|
|
|
+ .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
|
|
|
+ .modulemode = MODULEMODE_HWCTRL,
|
|
|
+ },
|
|
|
+ },
|
|
|
+ .dev_attr = ocp2scp_dev_attr,
|
|
|
+};
|
|
|
+
|
|
|
+/*
|
|
|
+ * 'prcm' class
|
|
|
+ * power and reset manager (part of the prcm infrastructure) + clock manager 2
|
|
|
+ * + clock manager 1 (in always on power domain) + local prm in mpu
|
|
|
+ */
|
|
|
+
|
|
|
+static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
|
|
|
+ .name = "prcm",
|
|
|
+};
|
|
|
+
|
|
|
+/* prcm_mpu */
|
|
|
+static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
|
|
|
+ .name = "prcm_mpu",
|
|
|
+ .class = &omap44xx_prcm_hwmod_class,
|
|
|
+ .clkdm_name = "l4_wkup_clkdm",
|
|
|
+ .flags = HWMOD_NO_IDLEST,
|
|
|
+ .prcm = {
|
|
|
+ .omap4 = {
|
|
|
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
|
|
+ },
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+/* cm_core_aon */
|
|
|
+static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
|
|
|
+ .name = "cm_core_aon",
|
|
|
+ .class = &omap44xx_prcm_hwmod_class,
|
|
|
+ .flags = HWMOD_NO_IDLEST,
|
|
|
+ .prcm = {
|
|
|
+ .omap4 = {
|
|
|
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
|
|
+ },
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+/* cm_core */
|
|
|
+static struct omap_hwmod omap44xx_cm_core_hwmod = {
|
|
|
+ .name = "cm_core",
|
|
|
+ .class = &omap44xx_prcm_hwmod_class,
|
|
|
+ .flags = HWMOD_NO_IDLEST,
|
|
|
+ .prcm = {
|
|
|
+ .omap4 = {
|
|
|
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
|
|
+ },
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+/* prm */
|
|
|
+static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
|
|
|
+ { .irq = 11 + OMAP44XX_IRQ_GIC_START },
|
|
|
+ { .irq = -1 }
|
|
|
+};
|
|
|
+
|
|
|
+static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
|
|
|
+ { .name = "rst_global_warm_sw", .rst_shift = 0 },
|
|
|
+ { .name = "rst_global_cold_sw", .rst_shift = 1 },
|
|
|
+};
|
|
|
+
|
|
|
+static struct omap_hwmod omap44xx_prm_hwmod = {
|
|
|
+ .name = "prm",
|
|
|
+ .class = &omap44xx_prcm_hwmod_class,
|
|
|
+ .mpu_irqs = omap44xx_prm_irqs,
|
|
|
+ .rst_lines = omap44xx_prm_resets,
|
|
|
+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
|
|
|
+};
|
|
|
+
|
|
|
+/*
|
|
|
+ * 'scrm' class
|
|
|
+ * system clock and reset manager
|
|
|
+ */
|
|
|
+
|
|
|
+static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
|
|
|
+ .name = "scrm",
|
|
|
+};
|
|
|
+
|
|
|
+/* scrm */
|
|
|
+static struct omap_hwmod omap44xx_scrm_hwmod = {
|
|
|
+ .name = "scrm",
|
|
|
+ .class = &omap44xx_scrm_hwmod_class,
|
|
|
+ .clkdm_name = "l4_wkup_clkdm",
|
|
|
+ .prcm = {
|
|
|
+ .omap4 = {
|
|
|
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
|
|
+ },
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+/*
|
|
|
+ * 'sl2if' class
|
|
|
+ * shared level 2 memory interface
|
|
|
+ */
|
|
|
+
|
|
|
+static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
|
|
|
+ .name = "sl2if",
|
|
|
+};
|
|
|
+
|
|
|
+/* sl2if */
|
|
|
+static struct omap_hwmod omap44xx_sl2if_hwmod = {
|
|
|
+ .name = "sl2if",
|
|
|
+ .class = &omap44xx_sl2if_hwmod_class,
|
|
|
+ .clkdm_name = "ivahd_clkdm",
|
|
|
+ .prcm = {
|
|
|
+ .omap4 = {
|
|
|
+ .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
|
|
|
+ .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
|
|
|
+ .modulemode = MODULEMODE_HWCTRL,
|
|
|
+ },
|
|
|
+ },
|