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@@ -819,3 +819,63 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
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OMAP24XX_CLKSEL_GPT5_MASK,
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OMAP24XX_CLKSEL_GPT5_MASK,
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OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
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OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
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OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait,
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OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait,
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+ gpt10_fck_parent_names, dss1_fck_ops);
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+
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+static struct clk gpt5_ick;
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+
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+static struct clk_hw_omap gpt5_ick_hw = {
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+ .hw = {
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+ .clk = &gpt5_ick,
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+ },
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+ .ops = &clkhwops_iclk_wait,
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+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
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+ .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
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+ .clkdm_name = "core_l4_clkdm",
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+};
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+
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+DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops);
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+
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+DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
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+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
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+ OMAP24XX_CLKSEL_GPT6_MASK,
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+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
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+ OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait,
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+ gpt10_fck_parent_names, dss1_fck_ops);
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+
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+static struct clk gpt6_ick;
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+
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+static struct clk_hw_omap gpt6_ick_hw = {
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+ .hw = {
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+ .clk = &gpt6_ick,
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+ },
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+ .ops = &clkhwops_iclk_wait,
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+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
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+ .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
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+ .clkdm_name = "core_l4_clkdm",
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+};
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+
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+DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops);
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+
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+DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
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+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
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+ OMAP24XX_CLKSEL_GPT7_MASK,
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+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
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+ OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait,
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+ gpt10_fck_parent_names, dss1_fck_ops);
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+
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+static struct clk gpt7_ick;
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+
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+static struct clk_hw_omap gpt7_ick_hw = {
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+ .hw = {
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+ .clk = &gpt7_ick,
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+ },
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+ .ops = &clkhwops_iclk_wait,
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+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
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+ .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
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+ .clkdm_name = "core_l4_clkdm",
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+};
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+
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+DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops);
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+
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+static struct clk gpt8_fck;
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+
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