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@@ -3114,3 +3114,91 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
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.addr = am33xx_tpcc_addr_space,
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.user = OCP_USER_MPU,
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};
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+
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+/* l3 main -> tpcc0 */
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+static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
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+ {
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+ .pa_start = 0x49800000,
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+ .pa_end = 0x49800000 + SZ_8K - 1,
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+ .flags = ADDR_TYPE_RT,
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+ },
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+ { }
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+};
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+
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+static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
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+ .master = &am33xx_l3_main_hwmod,
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+ .slave = &am33xx_tptc0_hwmod,
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+ .clk = "l3_gclk",
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+ .addr = am33xx_tptc0_addr_space,
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+ .user = OCP_USER_MPU,
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+};
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+
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+/* l3 main -> tpcc1 */
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+static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
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+ {
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+ .pa_start = 0x49900000,
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+ .pa_end = 0x49900000 + SZ_8K - 1,
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+ .flags = ADDR_TYPE_RT,
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+ },
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+ { }
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+};
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+
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+static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
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+ .master = &am33xx_l3_main_hwmod,
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+ .slave = &am33xx_tptc1_hwmod,
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+ .clk = "l3_gclk",
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+ .addr = am33xx_tptc1_addr_space,
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+ .user = OCP_USER_MPU,
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+};
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+
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+/* l3 main -> tpcc2 */
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+static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
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+ {
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+ .pa_start = 0x49a00000,
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+ .pa_end = 0x49a00000 + SZ_8K - 1,
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+ .flags = ADDR_TYPE_RT,
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+ },
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+ { }
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+};
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+
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+static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
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+ .master = &am33xx_l3_main_hwmod,
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+ .slave = &am33xx_tptc2_hwmod,
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+ .clk = "l3_gclk",
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+ .addr = am33xx_tptc2_addr_space,
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+ .user = OCP_USER_MPU,
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+};
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+
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+/* l4 wkup -> uart1 */
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+static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
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+ {
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+ .pa_start = 0x44E09000,
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+ .pa_end = 0x44E09000 + SZ_8K - 1,
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+ .flags = ADDR_TYPE_RT,
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+ },
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+ { }
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+};
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+
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+static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
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+ .master = &am33xx_l4_wkup_hwmod,
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+ .slave = &am33xx_uart1_hwmod,
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+ .clk = "dpll_core_m4_div2_ck",
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+ .addr = am33xx_uart1_addr_space,
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+ .user = OCP_USER_MPU,
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+};
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+
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+/* l4 ls -> uart2 */
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+static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
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+ {
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+ .pa_start = 0x48022000,
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+ .pa_end = 0x48022000 + SZ_8K - 1,
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+ .flags = ADDR_TYPE_RT,
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+ },
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+ { }
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+};
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+
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+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
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+ .master = &am33xx_l4_ls_hwmod,
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+ .slave = &am33xx_uart2_hwmod,
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+ .clk = "l4ls_gclk",
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+ .addr = am33xx_uart2_addr_space,
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