efElectricAgingTrendMining memoryOperation.h 岳彩东 commit at 2020-11-16

efElectricAgingTrendMining/dataSharedMemory/memoryOperation.h

@@ -986,3 +986,91 @@
 
 /*
  * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
+ * PRM_LDO_SRAM_MPU_CTRL
+ */
+#define OMAP4430_RETMODE_ENABLE_SHIFT					0
+#define OMAP4430_RETMODE_ENABLE_MASK					(1 << 0)
+
+/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */
+#define OMAP4430_RST1_SHIFT						0
+#define OMAP4430_RST1_MASK						(1 << 0)
+
+/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */
+#define OMAP4430_RST1ST_SHIFT						0
+#define OMAP4430_RST1ST_MASK						(1 << 0)
+
+/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */
+#define OMAP4430_RST2_SHIFT						1
+#define OMAP4430_RST2_MASK						(1 << 1)
+
+/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */
+#define OMAP4430_RST2ST_SHIFT						1
+#define OMAP4430_RST2ST_MASK						(1 << 1)
+
+/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */
+#define OMAP4430_RST3_SHIFT						2
+#define OMAP4430_RST3_MASK						(1 << 2)
+
+/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */
+#define OMAP4430_RST3ST_SHIFT						2
+#define OMAP4430_RST3ST_MASK						(1 << 2)
+
+/* Used by PRM_RSTTIME */
+#define OMAP4430_RSTTIME1_SHIFT						0
+#define OMAP4430_RSTTIME1_MASK						(0x3ff << 0)
+
+/* Used by PRM_RSTTIME */
+#define OMAP4430_RSTTIME2_SHIFT						10
+#define OMAP4430_RSTTIME2_MASK						(0x1f << 10)
+
+/* Used by PRM_RSTCTRL */
+#define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT				1
+#define OMAP4430_RST_GLOBAL_COLD_SW_MASK				(1 << 1)
+
+/* Used by PRM_RSTCTRL */
+#define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT				0
+#define OMAP4430_RST_GLOBAL_WARM_SW_MASK				(1 << 0)
+
+/* Used by REVISION_PRM */
+#define OMAP4430_R_RTL_SHIFT						11
+#define OMAP4430_R_RTL_MASK						(0x1f << 11)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_SA_VDD_CORE_L_SHIFT					0
+#define OMAP4430_SA_VDD_CORE_L_MASK					(1 << 0)
+
+/* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */
+#define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT				0
+#define OMAP4430_SA_VDD_CORE_L_0_6_MASK					(0x7f << 0)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_SA_VDD_IVA_L_SHIFT					8
+#define OMAP4430_SA_VDD_IVA_L_MASK					(1 << 8)
+
+/* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */
+#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT			8
+#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK			(0x7f << 8)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_SA_VDD_MPU_L_SHIFT					16
+#define OMAP4430_SA_VDD_MPU_L_MASK					(1 << 16)
+
+/* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */
+#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT			16
+#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK			(0x7f << 16)
+
+/* Used by REVISION_PRM */
+#define OMAP4430_SCHEME_SHIFT						30
+#define OMAP4430_SCHEME_MASK						(0x3 << 30)
+
+/* Used by PRM_VC_CFG_I2C_CLK */
+#define OMAP4430_SCLH_SHIFT						0
+#define OMAP4430_SCLH_MASK						(0xff << 0)
+
+/* Used by PRM_VC_CFG_I2C_CLK */
+#define OMAP4430_SCLL_SHIFT						8
+#define OMAP4430_SCLL_MASK						(0xff << 8)
+
+/* Used by PRM_RSTST */
+#define OMAP4430_SECURE_WDT_RST_SHIFT					4
+#define OMAP4430_SECURE_WDT_RST_MASK					(1 << 4)