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+/* linux/arch/arm/plat-s3c24xx/clock.c
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+ *
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+ * Copyright 2004-2005 Simtec Electronics
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+ * Ben Dooks <ben@simtec.co.uk>
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+ *
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+ * S3C24XX Core clock control support
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+ *
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+ * Based on, and code from linux/arch/arm/mach-versatile/clock.c
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+ **
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+ ** Copyright (C) 2004 ARM Limited.
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+ ** Written by Deep Blue Solutions Limited.
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+ *
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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+*/
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+
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+#include <linux/init.h>
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+#include <linux/module.h>
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+#include <linux/kernel.h>
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+#include <linux/list.h>
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+#include <linux/errno.h>
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+#include <linux/err.h>
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+#include <linux/platform_device.h>
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+#include <linux/device.h>
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+#include <linux/interrupt.h>
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+#include <linux/ioport.h>
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+#include <linux/clk.h>
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+#include <linux/spinlock.h>
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+#include <linux/io.h>
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+#if defined(CONFIG_DEBUG_FS)
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+#include <linux/debugfs.h>
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+#endif
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+
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+#include <mach/hardware.h>
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+#include <asm/irq.h>
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+
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+#include <plat/cpu-freq.h>
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+
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+#include <plat/clock.h>
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+#include <plat/cpu.h>
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+
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+#include <linux/serial_core.h>
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+#include <plat/regs-serial.h> /* for s3c24xx_uart_devs */
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+
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+/* clock information */
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+
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+static LIST_HEAD(clocks);
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+
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+/* We originally used an mutex here, but some contexts (see resume)
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+ * are calling functions such as clk_set_parent() with IRQs disabled
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+ * causing an BUG to be triggered.
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+ */
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+DEFINE_SPINLOCK(clocks_lock);
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+
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+/* Global watchdog clock used by arch_wtd_reset() callback */
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+struct clk *s3c2410_wdtclk;
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+static int __init s3c_wdt_reset_init(void)
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+{
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+ s3c2410_wdtclk = clk_get(NULL, "watchdog");
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+ if (IS_ERR(s3c2410_wdtclk))
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+ printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
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+ return 0;
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+}
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+arch_initcall(s3c_wdt_reset_init);
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+
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+/* enable and disable calls for use with the clk struct */
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+
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+static int clk_null_enable(struct clk *clk, int enable)
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+{
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+ return 0;
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+}
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+
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+int clk_enable(struct clk *clk)
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+{
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+ unsigned long flags;
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+
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+ if (IS_ERR(clk) || clk == NULL)
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+ return -EINVAL;
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+
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+ clk_enable(clk->parent);
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+
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+ spin_lock_irqsave(&clocks_lock, flags);
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+
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+ if ((clk->usage++) == 0)
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+ (clk->enable)(clk, 1);
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+
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+ spin_unlock_irqrestore(&clocks_lock, flags);
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+ return 0;
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+}
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+
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+void clk_disable(struct clk *clk)
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+{
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+ unsigned long flags;
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+
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+ if (IS_ERR(clk) || clk == NULL)
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+ return;
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+
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+ spin_lock_irqsave(&clocks_lock, flags);
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+
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+ if ((--clk->usage) == 0)
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+ (clk->enable)(clk, 0);
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+
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+ spin_unlock_irqrestore(&clocks_lock, flags);
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+ clk_disable(clk->parent);
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+}
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+
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+
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+unsigned long clk_get_rate(struct clk *clk)
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+{
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+ if (IS_ERR_OR_NULL(clk))
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+ return 0;
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+
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+ if (clk->rate != 0)
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+ return clk->rate;
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+
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+ if (clk->ops != NULL && clk->ops->get_rate != NULL)
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+ return (clk->ops->get_rate)(clk);
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+
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+ if (clk->parent != NULL)
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+ return clk_get_rate(clk->parent);
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+
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+ return clk->rate;
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+}
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+
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+long clk_round_rate(struct clk *clk, unsigned long rate)
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+{
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+ if (!IS_ERR_OR_NULL(clk) && clk->ops && clk->ops->round_rate)
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+ return (clk->ops->round_rate)(clk, rate);
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+
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+ return rate;
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+}
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+
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+int clk_set_rate(struct clk *clk, unsigned long rate)
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+{
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+ unsigned long flags;
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+ int ret;
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+
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+ if (IS_ERR_OR_NULL(clk))
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+ return -EINVAL;
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+
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+ /* We do not default just do a clk->rate = rate as
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+ * the clock may have been made this way by choice.
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+ */
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+
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