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@@ -737,3 +737,33 @@ DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
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OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait,
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OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait,
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gpt10_fck_parent_names, gpt1_fck_ops);
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gpt10_fck_parent_names, gpt1_fck_ops);
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+static struct clk gpt1_ick;
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+
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+static struct clk_hw_omap gpt1_ick_hw = {
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+ .hw = {
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+ .clk = &gpt1_ick,
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+ },
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+ .ops = &clkhwops_iclk_wait,
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+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
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+ .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
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+ .clkdm_name = "wkup_clkdm",
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+};
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+
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+DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops);
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+
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+DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
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+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
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+ OMAP24XX_CLKSEL_GPT2_MASK,
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+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
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+ OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait,
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+ gpt10_fck_parent_names, dss1_fck_ops);
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+
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+static struct clk gpt2_ick;
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+
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+static struct clk_hw_omap gpt2_ick_hw = {
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+ .hw = {
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+ .clk = &gpt2_ick,
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+ },
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+ .ops = &clkhwops_iclk_wait,
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+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
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+ .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
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