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@@ -406,3 +406,78 @@ void omap1_pm_suspend(void)
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MPUI1610_RESTORE(OMAP_IH2_3_MIR);
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MPUI1610_RESTORE(OMAP_IH2_3_MIR);
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}
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}
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+ if (!cpu_is_omap15xx())
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+ omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
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+
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+ /*
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+ * Re-enable interrupts
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+ */
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+
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+ local_irq_enable();
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+ local_fiq_enable();
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+
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+ omap_serial_wake_trigger(0);
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+
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+ printk(KERN_INFO "PM: OMAP%x is re-starting from deep sleep...\n",
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+ omap_rev());
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+}
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+
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+#if defined(DEBUG) && defined(CONFIG_PROC_FS)
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+static int g_read_completed;
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+
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+/*
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+ * Read system PM registers for debugging
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+ */
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+static int omap_pm_read_proc(
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+ char *page_buffer,
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+ char **my_first_byte,
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+ off_t virtual_start,
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+ int length,
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+ int *eof,
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+ void *data)
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+{
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+ int my_buffer_offset = 0;
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+ char * const my_base = page_buffer;
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+
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+ ARM_SAVE(ARM_CKCTL);
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+ ARM_SAVE(ARM_IDLECT1);
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+ ARM_SAVE(ARM_IDLECT2);
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+ if (!(cpu_is_omap15xx()))
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+ ARM_SAVE(ARM_IDLECT3);
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+ ARM_SAVE(ARM_EWUPCT);
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+ ARM_SAVE(ARM_RSTCT1);
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+ ARM_SAVE(ARM_RSTCT2);
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+ ARM_SAVE(ARM_SYSST);
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+
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+ ULPD_SAVE(ULPD_IT_STATUS);
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+ ULPD_SAVE(ULPD_CLOCK_CTRL);
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+ ULPD_SAVE(ULPD_SOFT_REQ);
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+ ULPD_SAVE(ULPD_STATUS_REQ);
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+ ULPD_SAVE(ULPD_DPLL_CTRL);
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+ ULPD_SAVE(ULPD_POWER_CTRL);
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+
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+ if (cpu_is_omap7xx()) {
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+ MPUI7XX_SAVE(MPUI_CTRL);
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+ MPUI7XX_SAVE(MPUI_DSP_STATUS);
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+ MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
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+ MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
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+ MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
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+ MPUI7XX_SAVE(EMIFS_CONFIG);
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+ } else if (cpu_is_omap15xx()) {
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+ MPUI1510_SAVE(MPUI_CTRL);
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+ MPUI1510_SAVE(MPUI_DSP_STATUS);
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+ MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
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+ MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
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+ MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
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+ MPUI1510_SAVE(EMIFS_CONFIG);
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+ } else if (cpu_is_omap16xx()) {
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+ MPUI1610_SAVE(MPUI_CTRL);
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+ MPUI1610_SAVE(MPUI_DSP_STATUS);
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+ MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
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+ MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
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+ MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
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+ MPUI1610_SAVE(EMIFS_CONFIG);
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+ }
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+
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+ if (virtual_start == 0) {
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+ g_read_completed = 0;
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