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@@ -555,3 +555,98 @@
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/*
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* clkpwr_irda_clk_ctrl register definitions
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+ */
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+#define LPC32XX_CLKPWR_IRDA_Y_DIV(y) ((y) & 0xFF)
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+#define LPC32XX_CLKPWR_IRDA_X_DIV(x) (((x) & 0xFF) << 8)
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+
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+/*
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+ * clkpwr_uart_clk_ctrl register definitions
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+ */
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+#define LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN _BIT(3)
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+#define LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN _BIT(2)
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+#define LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN _BIT(1)
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+#define LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN _BIT(0)
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+
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+/*
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+ * clkpwr_dmaclk_ctrl register definitions
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+ */
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+#define LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN 0x1
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+
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+/*
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+ * clkpwr_autoclock register definitions
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+ */
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+#define LPC32XX_CLKPWR_AUTOCLK_USB_EN 0x40
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+#define LPC32XX_CLKPWR_AUTOCLK_IRAM_EN 0x02
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+#define LPC32XX_CLKPWR_AUTOCLK_IROM_EN 0x01
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+
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+/*
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+ * Interrupt controller register offsets
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+ */
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+#define LPC32XX_INTC_MASK(x) io_p2v((x) + 0x00)
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+#define LPC32XX_INTC_RAW_STAT(x) io_p2v((x) + 0x04)
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+#define LPC32XX_INTC_STAT(x) io_p2v((x) + 0x08)
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+#define LPC32XX_INTC_POLAR(x) io_p2v((x) + 0x0C)
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+#define LPC32XX_INTC_ACT_TYPE(x) io_p2v((x) + 0x10)
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+#define LPC32XX_INTC_TYPE(x) io_p2v((x) + 0x14)
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+
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+/*
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+ * Timer/counter register offsets
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+ */
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+#define LPC32XX_TIMER_IR(x) io_p2v((x) + 0x00)
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+#define LPC32XX_TIMER_TCR(x) io_p2v((x) + 0x04)
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+#define LPC32XX_TIMER_TC(x) io_p2v((x) + 0x08)
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+#define LPC32XX_TIMER_PR(x) io_p2v((x) + 0x0C)
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+#define LPC32XX_TIMER_PC(x) io_p2v((x) + 0x10)
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+#define LPC32XX_TIMER_MCR(x) io_p2v((x) + 0x14)
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+#define LPC32XX_TIMER_MR0(x) io_p2v((x) + 0x18)
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+#define LPC32XX_TIMER_MR1(x) io_p2v((x) + 0x1C)
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+#define LPC32XX_TIMER_MR2(x) io_p2v((x) + 0x20)
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+#define LPC32XX_TIMER_MR3(x) io_p2v((x) + 0x24)
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+#define LPC32XX_TIMER_CCR(x) io_p2v((x) + 0x28)
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+#define LPC32XX_TIMER_CR0(x) io_p2v((x) + 0x2C)
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+#define LPC32XX_TIMER_CR1(x) io_p2v((x) + 0x30)
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+#define LPC32XX_TIMER_CR2(x) io_p2v((x) + 0x34)
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+#define LPC32XX_TIMER_CR3(x) io_p2v((x) + 0x38)
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+#define LPC32XX_TIMER_EMR(x) io_p2v((x) + 0x3C)
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+#define LPC32XX_TIMER_CTCR(x) io_p2v((x) + 0x70)
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+
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+/*
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+ * ir register definitions
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+ */
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+#define LPC32XX_TIMER_CNTR_MTCH_BIT(n) (1 << ((n) & 0x3))
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+#define LPC32XX_TIMER_CNTR_CAPT_BIT(n) (1 << (4 + ((n) & 0x3)))
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+
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+/*
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+ * tcr register definitions
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+ */
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+#define LPC32XX_TIMER_CNTR_TCR_EN 0x1
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+#define LPC32XX_TIMER_CNTR_TCR_RESET 0x2
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+
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+/*
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+ * mcr register definitions
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+ */
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+#define LPC32XX_TIMER_CNTR_MCR_MTCH(n) (0x1 << ((n) * 3))
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+#define LPC32XX_TIMER_CNTR_MCR_RESET(n) (0x1 << (((n) * 3) + 1))
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+#define LPC32XX_TIMER_CNTR_MCR_STOP(n) (0x1 << (((n) * 3) + 2))
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+
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+/*
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+ * Standard UART register offsets
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+ */
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+#define LPC32XX_UART_DLL_FIFO(x) io_p2v((x) + 0x00)
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+#define LPC32XX_UART_DLM_IER(x) io_p2v((x) + 0x04)
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+#define LPC32XX_UART_IIR_FCR(x) io_p2v((x) + 0x08)
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+#define LPC32XX_UART_LCR(x) io_p2v((x) + 0x0C)
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+#define LPC32XX_UART_MODEM_CTRL(x) io_p2v((x) + 0x10)
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+#define LPC32XX_UART_LSR(x) io_p2v((x) + 0x14)
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+#define LPC32XX_UART_MODEM_STATUS(x) io_p2v((x) + 0x18)
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+#define LPC32XX_UART_RXLEV(x) io_p2v((x) + 0x1C)
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+
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+/*
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+ * UART control structure offsets
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+ */
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+#define _UCREG(x) io_p2v(\
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+ LPC32XX_UART_CTRL_BASE + (x))
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+#define LPC32XX_UARTCTL_CTRL _UCREG(0x00)
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+#define LPC32XX_UARTCTL_CLKMODE _UCREG(0x04)
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+#define LPC32XX_UARTCTL_CLOOP _UCREG(0x08)
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+
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李欣儒