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+/*
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+ * opp2xxx.h - macros for old-style OMAP2xxx "OPP" definitions
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+ *
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+ * Copyright (C) 2005-2009 Texas Instruments, Inc.
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+ * Copyright (C) 2004-2009 Nokia Corporation
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+ *
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+ * Richard Woodruff <r-woodruff2@ti.com>
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+ *
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+ * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
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+ * These configurations are characterized by voltage and speed for clocks.
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+ * The device is only validated for certain combinations. One way to express
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+ * these combinations is via the 'ratio's' which the clocks operate with
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+ * respect to each other. These ratio sets are for a given voltage/DPLL
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+ * setting. All configurations can be described by a DPLL setting and a ratio
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+ * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
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+ *
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+ * 2430 differs from 2420 in that there are no more phase synchronizers used.
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+ * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
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+ * 2430 (iva2.1, NOdsp, mdm)
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+ *
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+ * XXX Missing voltage data.
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+ *
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+ * THe format described in this file is deprecated. Once a reasonable
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+ * OPP API exists, the data in this file should be converted to use it.
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+ *
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+ * This is technically part of the OMAP2xxx clock code.
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+ */
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+
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+#ifndef __ARCH_ARM_MACH_OMAP2_OPP2XXX_H
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+#define __ARCH_ARM_MACH_OMAP2_OPP2XXX_H
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+
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+/**
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+ * struct prcm_config - define clock rates on a per-OPP basis (24xx)
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+ *
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+ * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
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+ * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
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+ * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
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+ *
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+ * This is deprecated. As soon as we have a decent OPP API, we should
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+ * move all this stuff to it.
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+ */
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+struct prcm_config {
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+ unsigned long xtal_speed; /* crystal rate */
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+ unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
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+ unsigned long mpu_speed; /* speed of MPU */
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+ unsigned long cm_clksel_mpu; /* mpu divider */
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+ unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
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+ unsigned long cm_clksel_gfx; /* gfx dividers */
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+ unsigned long cm_clksel1_core; /* major subsystem dividers */
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+ unsigned long cm_clksel1_pll; /* m,n */
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+ unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
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+ unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
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+ unsigned long base_sdrc_rfr; /* base refresh timing for a set */
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+ unsigned short flags;
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+};
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+
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+
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吉超博