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@@ -386,3 +386,72 @@
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#define OMAP4430_CM_L4PER_I2C4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b8)
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#define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET 0x00c0
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#define OMAP4430_CM_L4PER_L4PER_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00c0)
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+#define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET 0x00d0
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+#define OMAP4430_CM_L4PER_MCASP2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d0)
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+#define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET 0x00d8
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+#define OMAP4430_CM_L4PER_MCASP3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d8)
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+#define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET 0x00e0
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+#define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e0)
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+#define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET 0x00e8
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+#define OMAP4430_CM_L4PER_MGATE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e8)
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+#define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0
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+#define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f0)
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+#define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8
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+#define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f8)
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+#define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100
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+#define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0100)
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+#define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108
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+#define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0108)
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+#define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET 0x0120
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+#define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0120)
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+#define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET 0x0128
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+#define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0128)
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+#define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET 0x0130
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+#define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0130)
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+#define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET 0x0138
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+#define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0138)
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+#define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140
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+#define OMAP4430_CM_L4PER_UART1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0140)
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+#define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148
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+#define OMAP4430_CM_L4PER_UART2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0148)
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+#define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150
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+#define OMAP4430_CM_L4PER_UART3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0150)
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+#define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158
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+#define OMAP4430_CM_L4PER_UART4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0158)
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+#define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET 0x0160
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+#define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0160)
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+#define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0168
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+#define OMAP4430_CM_L4PER_I2C5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0168)
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+#define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180
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+#define OMAP4430_CM_L4SEC_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0180)
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+#define OMAP4_CM_L4SEC_STATICDEP_OFFSET 0x0184
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+#define OMAP4430_CM_L4SEC_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0184)
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+#define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188
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+#define OMAP4430_CM_L4SEC_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0188)
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+#define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0
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+#define OMAP4430_CM_L4SEC_AES1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a0)
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+#define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8
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+#define OMAP4430_CM_L4SEC_AES2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a8)
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+#define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0
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+#define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b0)
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+#define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET 0x01b8
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+#define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b8)
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+#define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0
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+#define OMAP4430_CM_L4SEC_RNG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c0)
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+#define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8
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+#define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c8)
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+#define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET 0x01d8
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+#define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01d8)
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+
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+/* CM2.CEFUSE_CM2 register offsets */
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+#define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000
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+#define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0000)
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+#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
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+#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020)
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+
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+/* Function prototypes */
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+extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
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+extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
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+extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
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+
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+#endif
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