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@@ -236,3 +236,79 @@ static int cpld_mmc_get_cd(int module)
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/* low == card present */
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/* low == card present */
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return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
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return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
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+}
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+
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+static int cpld_mmc_get_ro(int module)
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+{
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+ if (!cpld)
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+ return -ENXIO;
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+
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+ /* high == card's write protect switch active */
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+ return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
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+}
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+
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+static struct davinci_mmc_config dm365evm_mmc_config = {
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+ .get_cd = cpld_mmc_get_cd,
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+ .get_ro = cpld_mmc_get_ro,
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+ .wires = 4,
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+ .max_freq = 50000000,
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+ .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
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+ .version = MMC_CTLR_VERSION_2,
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+};
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+
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+static void dm365evm_emac_configure(void)
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+{
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+ /*
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+ * EMAC pins are multiplexed with GPIO and UART
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+ * Further details are available at the DM365 ARM
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+ * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
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+ */
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+ davinci_cfg_reg(DM365_EMAC_TX_EN);
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+ davinci_cfg_reg(DM365_EMAC_TX_CLK);
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+ davinci_cfg_reg(DM365_EMAC_COL);
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+ davinci_cfg_reg(DM365_EMAC_TXD3);
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+ davinci_cfg_reg(DM365_EMAC_TXD2);
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+ davinci_cfg_reg(DM365_EMAC_TXD1);
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+ davinci_cfg_reg(DM365_EMAC_TXD0);
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+ davinci_cfg_reg(DM365_EMAC_RXD3);
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+ davinci_cfg_reg(DM365_EMAC_RXD2);
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+ davinci_cfg_reg(DM365_EMAC_RXD1);
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+ davinci_cfg_reg(DM365_EMAC_RXD0);
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+ davinci_cfg_reg(DM365_EMAC_RX_CLK);
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+ davinci_cfg_reg(DM365_EMAC_RX_DV);
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+ davinci_cfg_reg(DM365_EMAC_RX_ER);
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+ davinci_cfg_reg(DM365_EMAC_CRS);
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+ davinci_cfg_reg(DM365_EMAC_MDIO);
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+ davinci_cfg_reg(DM365_EMAC_MDCLK);
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+
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+ /*
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+ * EMAC interrupts are multiplexed with GPIO interrupts
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+ * Details are available at the DM365 ARM
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+ * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
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+ */
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+ davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
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+ davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
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+ davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
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+ davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
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+}
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+
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+static void dm365evm_mmc_configure(void)
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+{
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+ /*
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+ * MMC/SD pins are multiplexed with GPIO and EMIF
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+ * Further details are available at the DM365 ARM
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+ * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
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+ */
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+ davinci_cfg_reg(DM365_SD1_CLK);
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+ davinci_cfg_reg(DM365_SD1_CMD);
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+ davinci_cfg_reg(DM365_SD1_DATA3);
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+ davinci_cfg_reg(DM365_SD1_DATA2);
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+ davinci_cfg_reg(DM365_SD1_DATA1);
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+ davinci_cfg_reg(DM365_SD1_DATA0);
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+}
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+
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+static struct tvp514x_platform_data tvp5146_pdata = {
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+ .clk_polarity = 0,
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+ .hs_polarity = 1,
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+ .vs_polarity = 1
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+};
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