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@@ -734,3 +734,84 @@
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#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
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#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
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#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
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+#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
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+#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
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+#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
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+#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
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+#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
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+#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
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+#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
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+#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
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+#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
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+#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
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+#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
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+
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+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
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+#define TOVL_ERR0 TOVF_ERR0
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+#define TOVL_ERR1 TOVF_ERR1
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+#define TOVL_ERR2 TOVF_ERR2
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+#define TOVL_ERR3 TOVF_ERR3
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+#define TOVL_ERR4 TOVF_ERR4
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+#define TOVL_ERR5 TOVF_ERR5
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+#define TOVL_ERR6 TOVF_ERR6
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+#define TOVL_ERR7 TOVF_ERR7
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+
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+/* TIMERx_CONFIG Masks */
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+#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
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+#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
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+#define EXT_CLK 0x0003 /* External Clock Mode */
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+#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
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+#define PERIOD_CNT 0x0008 /* Period Count */
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+#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
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+#define TIN_SEL 0x0020 /* Timer Input Select */
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+#define OUT_DIS 0x0040 /* Output Pad Disable */
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+#define CLK_SEL 0x0080 /* Timer Clock Select */
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+#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
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+#define EMU_RUN 0x0200 /* Emulation Behavior Select */
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+#define ERR_TYP 0xC000 /* Error Type */
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+
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+/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
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+/* EBIU_AMGCTL Masks */
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+#define AMCKEN 0x0001 /* Enable CLKOUT */
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+#define AMBEN_NONE 0x0000 /* All Banks Disabled */
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+#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
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+#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
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+#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
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+#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
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+
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+/* EBIU_AMBCTL0 Masks */
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+#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
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+#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
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+#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
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+#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
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+#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
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+#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
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+#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
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+#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
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+#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
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+#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
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+#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
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+#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
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+#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
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+#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
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+#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
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+#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
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+#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
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+#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
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+#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
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+#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
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+#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
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+#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
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+#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
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+#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
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+#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
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+#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
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+#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
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+#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
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+#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
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+#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
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+#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
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+#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
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+#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
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+#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
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+#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
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