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@@ -2343,3 +2343,160 @@ static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
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static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
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.master = &omap3xxx_l4_core_hwmod,
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+ .slave = &omap3xxx_uart1_hwmod,
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+ .clk = "uart1_ick",
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+ .addr = omap3xxx_uart1_addr_space,
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+/* L4 CORE -> UART2 interface */
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+static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
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+ {
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+ .pa_start = OMAP3_UART2_BASE,
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+ .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
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+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
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+ },
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+ { }
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+};
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+
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+static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
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+ .master = &omap3xxx_l4_core_hwmod,
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+ .slave = &omap3xxx_uart2_hwmod,
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+ .clk = "uart2_ick",
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+ .addr = omap3xxx_uart2_addr_space,
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+/* L4 PER -> UART3 interface */
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+static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
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+ {
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+ .pa_start = OMAP3_UART3_BASE,
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+ .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
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+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
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+ },
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+ { }
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+};
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+
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+static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
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+ .master = &omap3xxx_l4_per_hwmod,
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+ .slave = &omap3xxx_uart3_hwmod,
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+ .clk = "uart3_ick",
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+ .addr = omap3xxx_uart3_addr_space,
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+/* L4 PER -> UART4 interface */
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+static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
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+ {
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+ .pa_start = OMAP3_UART4_BASE,
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+ .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
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+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
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+ },
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+ { }
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+};
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+
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+static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
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+ .master = &omap3xxx_l4_per_hwmod,
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+ .slave = &omap36xx_uart4_hwmod,
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+ .clk = "uart4_ick",
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+ .addr = omap36xx_uart4_addr_space,
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+/* AM35xx: L4 CORE -> UART4 interface */
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+static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
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+ {
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+ .pa_start = OMAP3_UART4_AM35XX_BASE,
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+ .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
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+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
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+ },
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+ { }
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+};
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+
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+static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
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+ .master = &omap3xxx_l4_core_hwmod,
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+ .slave = &am35xx_uart4_hwmod,
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+ .clk = "uart4_ick",
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+ .addr = am35xx_uart4_addr_space,
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+/* L4 CORE -> I2C1 interface */
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+static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
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+ .master = &omap3xxx_l4_core_hwmod,
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+ .slave = &omap3xxx_i2c1_hwmod,
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+ .clk = "i2c1_ick",
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+ .addr = omap2_i2c1_addr_space,
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+ .fw = {
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+ .omap2 = {
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+ .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
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+ .l4_prot_group = 7,
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+ .flags = OMAP_FIREWALL_L4,
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+ }
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+ },
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+/* L4 CORE -> I2C2 interface */
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+static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
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+ .master = &omap3xxx_l4_core_hwmod,
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+ .slave = &omap3xxx_i2c2_hwmod,
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+ .clk = "i2c2_ick",
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+ .addr = omap2_i2c2_addr_space,
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+ .fw = {
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+ .omap2 = {
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+ .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
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+ .l4_prot_group = 7,
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+ .flags = OMAP_FIREWALL_L4,
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+ }
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+ },
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+/* L4 CORE -> I2C3 interface */
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+static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
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+ {
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+ .pa_start = 0x48060000,
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+ .pa_end = 0x48060000 + SZ_128 - 1,
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+ .flags = ADDR_TYPE_RT,
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+ },
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+ { }
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+};
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+
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+static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
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+ .master = &omap3xxx_l4_core_hwmod,
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+ .slave = &omap3xxx_i2c3_hwmod,
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+ .clk = "i2c3_ick",
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+ .addr = omap3xxx_i2c3_addr_space,
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+ .fw = {
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+ .omap2 = {
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+ .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
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+ .l4_prot_group = 7,
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+ .flags = OMAP_FIREWALL_L4,
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+ }
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+ },
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+/* L4 CORE -> SR1 interface */
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+static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
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+ {
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+ .pa_start = OMAP34XX_SR1_BASE,
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+ .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
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+ .flags = ADDR_TYPE_RT,
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+ },
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+ { }
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+};
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+
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+static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
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+ .master = &omap3xxx_l4_core_hwmod,
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+ .slave = &omap34xx_sr1_hwmod,
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+ .clk = "sr_l4_ick",
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+ .addr = omap3_sr1_addr_space,
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+ .user = OCP_USER_MPU,
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+};
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+
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+static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
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+ .master = &omap3xxx_l4_core_hwmod,
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+ .slave = &omap36xx_sr1_hwmod,
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+ .clk = "sr_l4_ick",
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