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@@ -97,3 +97,75 @@
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#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
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/* RTC Registers */
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+
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+#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
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+#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
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+#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
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+#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
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+#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
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+#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
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+#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
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+#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
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+#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
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+#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
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+#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
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+#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
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+
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+/* UART0 Registers */
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+
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+#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
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+#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
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+#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
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+#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
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+#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
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+#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
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+#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
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+#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
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+#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
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+#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
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+#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
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+#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
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+#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
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+#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
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+#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
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+#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
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+#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET)
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+#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val)
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+#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR)
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+#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
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+#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
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+#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
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+#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
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+#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
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+
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+/* SPI0 Registers */
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+
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+#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
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+#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
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+#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
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+#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
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+#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
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+#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
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+#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
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+#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
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+#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
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+#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
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+#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
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+#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
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+#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
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+#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
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+
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+/* Timer Groubfin_read_() of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
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+
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+/* Two Wire Interface Registers (TWI0) */
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+
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+/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
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+
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+/* SPORT1 Registers */
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+
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+#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
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+#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
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+#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
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+#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
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+#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
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+#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
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朱涛