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				@@ -53,3 +53,64 @@ 
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				  *   P7  ...  P0  A7 ... A0  A7 ... A0    
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				  * |    Page    | Addr MSB | Addr LSB |   (DMA registers) 
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				  * 
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				+ *  Address mapping for channels 5-7: 
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				+ * 
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				+ *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses) 
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				+ *    |  ...  |   \   \   ... \  \  \  ... \  \ 
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				+ *    |  ...  |    \   \   ... \  \  \  ... \  (not used) 
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				+ *    |  ...  |     \   \   ... \  \  \  ... \ 
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				+ *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0    
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				+ * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers) 
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				+ * 
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				+ * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses 
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				+ * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at 
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				+ * the hardware level, so odd-byte transfers aren't possible). 
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				+ * 
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				+ * Transfer count (_not # bytes_) is limited to 64K, represented as actual 
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				+ * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more, 
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				+ * and up to 128K bytes may be transferred on channels 5-7 in one operation.  
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				+ * 
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				+ */ 
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				+ 
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				+#define MAX_DMA_CHANNELS	8 
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				+ 
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				+/* 
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				+  ISA DMA limitations on Alpha platforms, 
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				+ 
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				+  These may be due to SIO (PCI<->ISA bridge) chipset limitation, or 
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				+  just a wiring limit. 
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				+*/ 
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				+ 
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				+/* The maximum address for ISA DMA transfer on Alpha XL, due to an 
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				+   hardware SIO limitation, is 64MB. 
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				+*/ 
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				+#define ALPHA_XL_MAX_ISA_DMA_ADDRESS		0x04000000UL 
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				+ 
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				+/* The maximum address for ISA DMA transfer on RUFFIAN, 
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				+   due to an hardware SIO limitation, is 16MB. 
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				+*/ 
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				+#define ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS	0x01000000UL 
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				+ 
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				+/* The maximum address for ISA DMA transfer on SABLE, and some ALCORs, 
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				+   due to an hardware SIO chip limitation, is 2GB. 
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				+*/ 
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				+#define ALPHA_SABLE_MAX_ISA_DMA_ADDRESS		0x80000000UL 
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				+#define ALPHA_ALCOR_MAX_ISA_DMA_ADDRESS		0x80000000UL 
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				+ 
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				+/* 
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				+  Maximum address for all the others is the complete 32-bit bus 
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				+  address space. 
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				+*/ 
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				+#define ALPHA_MAX_ISA_DMA_ADDRESS		0x100000000UL 
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				+ 
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				+#ifdef CONFIG_ALPHA_GENERIC 
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				+# define MAX_ISA_DMA_ADDRESS		(alpha_mv.max_isa_dma_address) 
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				+#else 
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				+# if defined(CONFIG_ALPHA_XL) 
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				+#  define MAX_ISA_DMA_ADDRESS		ALPHA_XL_MAX_ISA_DMA_ADDRESS 
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				+# elif defined(CONFIG_ALPHA_RUFFIAN) 
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				+#  define MAX_ISA_DMA_ADDRESS		ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS 
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				+# elif defined(CONFIG_ALPHA_SABLE) 
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				+#  define MAX_ISA_DMA_ADDRESS		ALPHA_SABLE_MAX_ISA_DMA_ADDRESS 
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				+# elif defined(CONFIG_ALPHA_ALCOR) 
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				+#  define MAX_ISA_DMA_ADDRESS		ALPHA_ALCOR_MAX_ISA_DMA_ADDRESS 
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