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@@ -56,3 +56,161 @@ extern void omap_writel(u32 v, u32 pa);
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/* Almost all documentation for chip and board memory maps assumes
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* BM is clear. Most devel boards have a switch to control booting
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* from NOR flash (using external chipselect 3) rather than mask ROM,
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+ * which uses BM to interchange the physical CS0 and CS3 addresses.
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+ */
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+static inline u32 omap_cs0m_phys(void)
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+{
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+ return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
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+ ? OMAP_CS3_PHYS : 0;
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+}
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+
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+static inline u32 omap_cs3_phys(void)
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+{
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+ return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
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+ ? 0 : OMAP_CS3_PHYS;
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+}
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+
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+#endif /* ifndef __ASSEMBLER__ */
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+
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+#define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
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+#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET)
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+
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+#include <mach/serial.h>
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+
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+/*
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+ * ---------------------------------------------------------------------------
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+ * Common definitions for all OMAP processors
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+ * NOTE: Put all processor or board specific parts to the special header
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+ * files.
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+ * ---------------------------------------------------------------------------
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+ */
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+
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+/*
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+ * ----------------------------------------------------------------------------
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+ * Timers
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+ * ----------------------------------------------------------------------------
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+ */
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+#define OMAP_MPU_TIMER1_BASE (0xfffec500)
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+#define OMAP_MPU_TIMER2_BASE (0xfffec600)
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+#define OMAP_MPU_TIMER3_BASE (0xfffec700)
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+#define MPU_TIMER_FREE (1 << 6)
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+#define MPU_TIMER_CLOCK_ENABLE (1 << 5)
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+#define MPU_TIMER_AR (1 << 1)
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+#define MPU_TIMER_ST (1 << 0)
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+
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+/*
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+ * ----------------------------------------------------------------------------
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+ * Clocks
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+ * ----------------------------------------------------------------------------
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+ */
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+#define CLKGEN_REG_BASE (0xfffece00)
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+#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
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+#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
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+#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
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+#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
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+#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
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+#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
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+#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
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+#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
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+
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+#define CK_RATEF 1
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+#define CK_IDLEF 2
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+#define CK_ENABLEF 4
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+#define CK_SELECTF 8
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+#define SETARM_IDLE_SHIFT
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+
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+/* DPLL control registers */
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+#define DPLL_CTL (0xfffecf00)
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+
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+/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
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+#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
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+#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
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+#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
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+#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
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+#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14)
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+
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+/*
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+ * ---------------------------------------------------------------------------
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+ * UPLD
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+ * ---------------------------------------------------------------------------
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+ */
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+#define ULPD_REG_BASE (0xfffe0800)
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+#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
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+#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
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+#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
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+# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */
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+# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */
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+#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
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+# define SOFT_UDC_REQ (1 << 4)
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+# define SOFT_USB_CLK_REQ (1 << 3)
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+# define SOFT_DPLL_REQ (1 << 0)
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+#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
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+#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
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+#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
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+#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
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+#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68)
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+# define DIS_MMC2_DPLL_REQ (1 << 11)
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+# define DIS_MMC1_DPLL_REQ (1 << 10)
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+# define DIS_UART3_DPLL_REQ (1 << 9)
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+# define DIS_UART2_DPLL_REQ (1 << 8)
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+# define DIS_UART1_DPLL_REQ (1 << 7)
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+# define DIS_USB_HOST_DPLL_REQ (1 << 6)
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+#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)
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+#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
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+
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+/*
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+ * ---------------------------------------------------------------------------
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+ * Watchdog timer
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+ * ---------------------------------------------------------------------------
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+ */
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+
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+/* Watchdog timer within the OMAP3.2 gigacell */
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+#define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
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+#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
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+#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
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+#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
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+#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)
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+
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+/*
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+ * ---------------------------------------------------------------------------
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+ * Interrupts
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+ * ---------------------------------------------------------------------------
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+ */
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+#ifdef CONFIG_ARCH_OMAP1
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+
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+/*
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+ * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
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+ * or something similar.. -- PFM.
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+ */
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+
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+#define OMAP_IH1_BASE 0xfffecb00
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+#define OMAP_IH2_BASE 0xfffe0000
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+
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+#define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00)
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+#define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04)
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+#define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10)
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+#define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14)
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+#define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18)
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+#define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c)
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+#define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c)
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+
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+#define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00)
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+#define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04)
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+#define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10)
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+#define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14)
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+#define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18)
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+#define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c)
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+#define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c)
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+
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+#define IRQ_ITR_REG_OFFSET 0x00
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+#define IRQ_MIR_REG_OFFSET 0x04
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+#define IRQ_SIR_IRQ_REG_OFFSET 0x10
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+#define IRQ_SIR_FIQ_REG_OFFSET 0x14
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+#define IRQ_CONTROL_REG_OFFSET 0x18
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+#define IRQ_ISR_REG_OFFSET 0x9c
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+#define IRQ_ILR0_REG_OFFSET 0x1c
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+#define IRQ_GMR_REG_OFFSET 0xa0
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+
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+#endif
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+
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+/*
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