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+#ifndef __ALPHA_MCPCIA__H__
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+#define __ALPHA_MCPCIA__H__
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+
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+/* Define to experiment with fitting everything into one 128MB HAE window.
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+ One window per bus, that is. */
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+#define MCPCIA_ONE_HAE_WINDOW 1
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+
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+#include <linux/types.h>
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+#include <asm/compiler.h>
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+#include <asm/mce.h>
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+
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+/*
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+ * MCPCIA is the internal name for a core logic chipset which provides
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+ * PCI access for the RAWHIDE family of systems.
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+ *
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+ * This file is based on:
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+ *
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+ * RAWHIDE System Programmer's Manual
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+ * 16-May-96
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+ * Rev. 1.4
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+ *
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+ */
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+
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+/*------------------------------------------------------------------------**
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+** **
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+** I/O procedures **
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+** **
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+** inport[b|w|t|l], outport[b|w|t|l] 8:16:24:32 IO xfers **
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+** inportbxt: 8 bits only **
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+** inport: alias of inportw **
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+** outport: alias of outportw **
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+** **
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+** inmem[b|w|t|l], outmem[b|w|t|l] 8:16:24:32 ISA memory xfers **
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+** inmembxt: 8 bits only **
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+** inmem: alias of inmemw **
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+** outmem: alias of outmemw **
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+** **
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+**------------------------------------------------------------------------*/
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+
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+
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+/* MCPCIA ADDRESS BIT DEFINITIONS
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+ *
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+ * 3333 3333 3322 2222 2222 1111 1111 11
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+ * 9876 5432 1098 7654 3210 9876 5432 1098 7654 3210
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+ * ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
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+ * 1 000
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+ * ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
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+ * | |\|
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+ * | Byte Enable --+ |
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+ * | Transfer Length --+
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+ * +-- IO space, not cached
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+ *
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+ * Byte Transfer
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+ * Enable Length Transfer Byte Address
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+ * adr<6:5> adr<4:3> Length Enable Adder
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+ * ---------------------------------------------
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+ * 00 00 Byte 1110 0x000
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+ * 01 00 Byte 1101 0x020
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+ * 10 00 Byte 1011 0x040
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+ * 11 00 Byte 0111 0x060
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+ *
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+ * 00 01 Word 1100 0x008
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+ * 01 01 Word 1001 0x028 <= Not supported in this code.
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+ * 10 01 Word 0011 0x048
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+ *
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+ * 00 10 Tribyte 1000 0x010
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+ * 01 10 Tribyte 0001 0x030
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+ *
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+ * 10 11 Longword 0000 0x058
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+ *
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+ * Note that byte enables are asserted low.
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+ *
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+ */
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+
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+#define MCPCIA_MAX_HOSES 4
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+
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+#define MCPCIA_MID(m) ((unsigned long)(m) << 33)
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+
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+/* Dodge has PCI0 and PCI1 at MID 4 and 5 respectively.
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+ Durango adds PCI2 and PCI3 at MID 6 and 7 respectively. */
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+#define MCPCIA_HOSE2MID(h) ((h) + 4)
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+
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+#define MCPCIA_MEM_MASK 0x07ffffff /* SPARSE Mem region mask is 27 bits */
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+
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+/*
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+ * Memory spaces:
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+ */
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+#define MCPCIA_SPARSE(m) (IDENT_ADDR + 0xf000000000UL + MCPCIA_MID(m))
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+#define MCPCIA_DENSE(m) (IDENT_ADDR + 0xf100000000UL + MCPCIA_MID(m))
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+#define MCPCIA_IO(m) (IDENT_ADDR + 0xf180000000UL + MCPCIA_MID(m))
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+#define MCPCIA_CONF(m) (IDENT_ADDR + 0xf1c0000000UL + MCPCIA_MID(m))
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+#define MCPCIA_CSR(m) (IDENT_ADDR + 0xf1e0000000UL + MCPCIA_MID(m))
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+#define MCPCIA_IO_IACK(m) (IDENT_ADDR + 0xf1f0000000UL + MCPCIA_MID(m))
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+#define MCPCIA_DENSE_IO(m) (IDENT_ADDR + 0xe1fc000000UL + MCPCIA_MID(m))
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+#define MCPCIA_DENSE_CONF(m) (IDENT_ADDR + 0xe1fe000000UL + MCPCIA_MID(m))
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+
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+/*
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+ * General Registers
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+ */
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+#define MCPCIA_REV(m) (MCPCIA_CSR(m) + 0x000)
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+#define MCPCIA_WHOAMI(m) (MCPCIA_CSR(m) + 0x040)
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+#define MCPCIA_PCI_LAT(m) (MCPCIA_CSR(m) + 0x080)
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+#define MCPCIA_CAP_CTRL(m) (MCPCIA_CSR(m) + 0x100)
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+#define MCPCIA_HAE_MEM(m) (MCPCIA_CSR(m) + 0x400)
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+#define MCPCIA_HAE_IO(m) (MCPCIA_CSR(m) + 0x440)
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+#define _MCPCIA_IACK_SC(m) (MCPCIA_CSR(m) + 0x480)
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+#define MCPCIA_HAE_DENSE(m) (MCPCIA_CSR(m) + 0x4C0)
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+
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+/*
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+ * Interrupt Control registers
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+ */
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+#define MCPCIA_INT_CTL(m) (MCPCIA_CSR(m) + 0x500)
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+#define MCPCIA_INT_REQ(m) (MCPCIA_CSR(m) + 0x540)
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+#define MCPCIA_INT_TARG(m) (MCPCIA_CSR(m) + 0x580)
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+#define MCPCIA_INT_ADR(m) (MCPCIA_CSR(m) + 0x5C0)
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+#define MCPCIA_INT_ADR_EXT(m) (MCPCIA_CSR(m) + 0x600)
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+#define MCPCIA_INT_MASK0(m) (MCPCIA_CSR(m) + 0x640)
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+#define MCPCIA_INT_MASK1(m) (MCPCIA_CSR(m) + 0x680)
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+#define MCPCIA_INT_ACK0(m) (MCPCIA_CSR(m) + 0x10003f00)
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+#define MCPCIA_INT_ACK1(m) (MCPCIA_CSR(m) + 0x10003f40)
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+
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+/*
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+ * Performance Monitor registers
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+ */
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+#define MCPCIA_PERF_MON(m) (MCPCIA_CSR(m) + 0x300)
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+#define MCPCIA_PERF_CONT(m) (MCPCIA_CSR(m) + 0x340)
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+
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+/*
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+ * Diagnostic Registers
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+ */
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+#define MCPCIA_CAP_DIAG(m) (MCPCIA_CSR(m) + 0x700)
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+#define MCPCIA_TOP_OF_MEM(m) (MCPCIA_CSR(m) + 0x7C0)
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+
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+/*
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+ * Error registers
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+ */
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+#define MCPCIA_MC_ERR0(m) (MCPCIA_CSR(m) + 0x800)
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+#define MCPCIA_MC_ERR1(m) (MCPCIA_CSR(m) + 0x840)
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+#define MCPCIA_CAP_ERR(m) (MCPCIA_CSR(m) + 0x880)
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+#define MCPCIA_PCI_ERR1(m) (MCPCIA_CSR(m) + 0x1040)
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+#define MCPCIA_MDPA_STAT(m) (MCPCIA_CSR(m) + 0x4000)
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+#define MCPCIA_MDPA_SYN(m) (MCPCIA_CSR(m) + 0x4040)
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+#define MCPCIA_MDPA_DIAG(m) (MCPCIA_CSR(m) + 0x4080)
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+#define MCPCIA_MDPB_STAT(m) (MCPCIA_CSR(m) + 0x8000)
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+#define MCPCIA_MDPB_SYN(m) (MCPCIA_CSR(m) + 0x8040)
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+#define MCPCIA_MDPB_DIAG(m) (MCPCIA_CSR(m) + 0x8080)
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+
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+/*
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+ * PCI Address Translation Registers.
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+ */
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+#define MCPCIA_SG_TBIA(m) (MCPCIA_CSR(m) + 0x1300)
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+#define MCPCIA_HBASE(m) (MCPCIA_CSR(m) + 0x1340)
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+
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+#define MCPCIA_W0_BASE(m) (MCPCIA_CSR(m) + 0x1400)
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+#define MCPCIA_W0_MASK(m) (MCPCIA_CSR(m) + 0x1440)
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+#define MCPCIA_T0_BASE(m) (MCPCIA_CSR(m) + 0x1480)
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+
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+#define MCPCIA_W1_BASE(m) (MCPCIA_CSR(m) + 0x1500)
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+#define MCPCIA_W1_MASK(m) (MCPCIA_CSR(m) + 0x1540)
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+#define MCPCIA_T1_BASE(m) (MCPCIA_CSR(m) + 0x1580)
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+
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+#define MCPCIA_W2_BASE(m) (MCPCIA_CSR(m) + 0x1600)
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+#define MCPCIA_W2_MASK(m) (MCPCIA_CSR(m) + 0x1640)
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+#define MCPCIA_T2_BASE(m) (MCPCIA_CSR(m) + 0x1680)
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+
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+#define MCPCIA_W3_BASE(m) (MCPCIA_CSR(m) + 0x1700)
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+#define MCPCIA_W3_MASK(m) (MCPCIA_CSR(m) + 0x1740)
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+#define MCPCIA_T3_BASE(m) (MCPCIA_CSR(m) + 0x1780)
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+
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+/* Hack! Only words for bus 0. */
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+
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+#ifndef MCPCIA_ONE_HAE_WINDOW
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+#define MCPCIA_HAE_ADDRESS MCPCIA_HAE_MEM(4)
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+#endif
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+#define MCPCIA_IACK_SC _MCPCIA_IACK_SC(4)
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+
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+/*
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+ * The canonical non-remaped I/O and MEM addresses have these values
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+ * subtracted out. This is arranged so that folks manipulating ISA
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+ * devices can use their familiar numbers and have them map to bus 0.
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+ */
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+
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+#define MCPCIA_IO_BIAS MCPCIA_IO(4)
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+#define MCPCIA_MEM_BIAS MCPCIA_DENSE(4)
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+
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王隽