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@@ -409,3 +409,112 @@ static struct clk *fsibckcr_parent[] = {
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[2] = &fsibck_clk, /* external input for FSI B */
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[3] = NULL, /* setting prohibited */
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};
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+
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+static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
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+ [DIV6_HDMI] = SH_CLK_DIV6_EXT(HDMICKCR, 0,
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+ hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
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+ [DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0,
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+ fsiackcr_parent, ARRAY_SIZE(fsiackcr_parent), 6, 2),
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+ [DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0,
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+ fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2),
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+};
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+
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+/* FSI DIV */
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+enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR };
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+
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+static struct clk fsidivs[] = {
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+ [FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]),
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+ [FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]),
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+};
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+
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+enum { MSTP001, MSTP000,
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+ MSTP131, MSTP130,
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+ MSTP129, MSTP128, MSTP127, MSTP126, MSTP125,
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+ MSTP118, MSTP117, MSTP116, MSTP113,
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+ MSTP106, MSTP101, MSTP100,
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+ MSTP223,
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+ MSTP218, MSTP217, MSTP216, MSTP214, MSTP208, MSTP207,
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+ MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
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+ MSTP328, MSTP323, MSTP322, MSTP315, MSTP314, MSTP313, MSTP312,
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+ MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP407, MSTP406,
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+ MSTP405, MSTP404, MSTP403, MSTP400,
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+ MSTP_NR };
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+
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+#define MSTP(_parent, _reg, _bit, _flags) \
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+ SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
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+
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+static struct clk mstp_clks[MSTP_NR] = {
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+ [MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
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+ [MSTP000] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 0, 0), /* MSIOF0 */
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+ [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
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+ [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
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+ [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
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+ [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
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+ [MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU */
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+ [MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2 */
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+ [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
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+ [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */
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+ [MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
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+ [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
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+ [MSTP113] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 13, 0), /* MERAM */
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+ [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
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+ [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
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+ [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
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+ [MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */
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+ [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */
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+ [MSTP217] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */
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+ [MSTP216] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 16, 0), /* DMAC3 */
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+ [MSTP214] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 14, 0), /* USBDMAC */
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+ [MSTP208] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 8, 0), /* MSIOF1 */
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+ [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
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+ [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
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+ [MSTP205] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 5, 0), /* MSIOF2 */
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+ [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
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+ [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
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+ [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
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+ [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
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+ [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
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+ [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSI2 */
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+ [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
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+ [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
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+ [MSTP315] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 15, 0), /* FLCTL*/
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+ [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
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+ [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
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+ [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */
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+ [MSTP423] = MSTP(&div4_clks[DIV4_B], SMSTPCR4, 23, 0), /* DSITX1 */
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+ [MSTP415] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */
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+ [MSTP413] = MSTP(&pllc1_div2_clk, SMSTPCR4, 13, 0), /* HDMI */
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+ [MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */
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+ [MSTP410] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 10, 0), /* IIC4 */
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+ [MSTP407] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 7, 0), /* USB-DMAC1 */
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+ [MSTP406] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 6, 0), /* USB1 */
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+ [MSTP405] = MSTP(&r_clk, SMSTPCR4, 5, 0), /* CMT4 */
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+ [MSTP404] = MSTP(&r_clk, SMSTPCR4, 4, 0), /* CMT3 */
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+ [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
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+ [MSTP400] = MSTP(&r_clk, SMSTPCR4, 0, 0), /* CMT2 */
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+};
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+
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+static struct clk_lookup lookups[] = {
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+ /* main clocks */
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+ CLKDEV_CON_ID("dv_clki_div2_clk", &sh7372_dv_clki_div2_clk),
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+ CLKDEV_CON_ID("r_clk", &r_clk),
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+ CLKDEV_CON_ID("extal1", &sh7372_extal1_clk),
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+ CLKDEV_CON_ID("extal2", &sh7372_extal2_clk),
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+ CLKDEV_CON_ID("extal1_div2_clk", &extal1_div2_clk),
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+ CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
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+ CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk),
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+ CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
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+ CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
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+ CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
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+ CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk),
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+ CLKDEV_CON_ID("fsiack", &fsiack_clk),
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+ CLKDEV_CON_ID("fsibck", &fsibck_clk),
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+
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+ /* DIV4 clocks */
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+ CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
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+ CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
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+ CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
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+ CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
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+ CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
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+ CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]),
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+ CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
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