|  | @@ -925,3 +925,64 @@
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				|  |  |  #define URX_RXDATA_SHIFT 0
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				|  |  |  #define URX_PARITY_ERROR 0x0100	/* Parity Error */
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				|  |  |  #define URX_BREAK	 0x0200	/* Break Detected */
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				|  |  | +#define URX_FRAME_ERROR	 0x0400	/* Framing Error */
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				|  |  | +#define URX_OVRUN	 0x0800	/* Serial Overrun */
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				|  |  | +#define URX_DATA_READY	 0x2000	/* Data Ready (FIFO not empty) */
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				|  |  | +#define URX_FIFO_HALF	 0x4000 /* FIFO is Half-Full */
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				|  |  | +#define URX_FIFO_FULL	 0x8000	/* FIFO is Full */
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				|  |  | +
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				|  |  | +/*
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				|  |  | + * UART Transmitter Register 
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				|  |  | + */
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				|  |  | +#define UTX_ADDR	0xfffff906
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				|  |  | +#define UTX		WORD_REF(UTX_ADDR)
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				|  |  | +
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				|  |  | +#define UTX_TXDATA_ADDR	0xfffff907
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				|  |  | +#define UTX_TXDATA	BYTE_REF(UTX_TXDATA_ADDR)
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				|  |  | +
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				|  |  | +#define UTX_TXDATA_MASK	 0x00ff	/* Data to be transmitted */
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				|  |  | +#define UTX_TXDATA_SHIFT 0
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				|  |  | +#define UTX_CTS_DELTA	 0x0100	/* CTS changed */
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				|  |  | +#define UTX_CTS_STATUS	 0x0200	/* CTS State */
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				|  |  | +#define	UTX_IGNORE_CTS	 0x0800	/* Ignore CTS */
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				|  |  | +#define UTX_SEND_BREAK	 0x1000	/* Send a BREAK */
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				|  |  | +#define UTX_TX_AVAIL	 0x2000	/* Transmit FIFO has a slot available */
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				|  |  | +#define UTX_FIFO_HALF	 0x4000	/* Transmit FIFO is half empty */
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				|  |  | +#define UTX_FIFO_EMPTY	 0x8000	/* Transmit FIFO is empty */
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				|  |  | +
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				|  |  | +/* 'EZ328-compatible definitions */
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				|  |  | +#define UTX_CTS_STAT	UTX_CTS_STATUS
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				|  |  | +#define UTX_NOCTS	UTX_IGNORE_CTS
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				|  |  | +
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				|  |  | +/*
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				|  |  | + * UART Miscellaneous Register 
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				|  |  | + */
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				|  |  | +#define UMISC_ADDR	0xfffff908
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				|  |  | +#define UMISC		WORD_REF(UMISC_ADDR)
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				|  |  | +
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				|  |  | +#define UMISC_TX_POL	 0x0004	/* Transmit Polarity */
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				|  |  | +#define UMISC_RX_POL	 0x0008	/* Receive Polarity */
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				|  |  | +#define UMISC_IRDA_LOOP	 0x0010	/* IrDA Loopback Enable */
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				|  |  | +#define UMISC_IRDA_EN	 0x0020	/* Infra-Red Enable */
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				|  |  | +#define UMISC_RTS	 0x0040	/* Set RTS status */
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				|  |  | +#define UMISC_RTSCONT	 0x0080	/* Choose RTS control */
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				|  |  | +#define UMISC_LOOP	 0x1000	/* Serial Loopback Enable */
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				|  |  | +#define UMISC_FORCE_PERR 0x2000	/* Force Parity Error */
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				|  |  | +#define UMISC_CLKSRC	 0x4000	/* Clock Source */
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				|  |  | +
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				|  |  | +
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				|  |  | +/* generalization of uart control registers to support multiple ports: */
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				|  |  | +typedef volatile struct {
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				|  |  | +  volatile unsigned short int ustcnt;
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				|  |  | +  volatile unsigned short int ubaud;
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				|  |  | +  union {
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				|  |  | +    volatile unsigned short int w;
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				|  |  | +    struct {
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				|  |  | +      volatile unsigned char status;
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				|  |  | +      volatile unsigned char rxdata;
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				|  |  | +    } b;
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				|  |  | +  } urx;
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				|  |  | +  union {
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				|  |  | +    volatile unsigned short int w;
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				|  |  | +    struct {
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				|  |  | +      volatile unsigned char status;
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