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@@ -465,3 +465,150 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
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if (gpio_is_valid(data->irq_pin)) {
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at91_set_gpio_input(data->irq_pin, 1);
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at91_set_deglitch(data->irq_pin, 1);
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+ }
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+
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+ if (gpio_is_valid(data->vcc_pin))
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+ /* initially off */
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+ at91_set_gpio_output(data->vcc_pin, 0);
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+
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+ /* enable EBI controlled pins */
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+ at91_set_A_periph(AT91_PIN_PD5, 1); /* NWAIT */
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+ at91_set_A_periph(AT91_PIN_PD8, 0); /* CFCE1 */
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+ at91_set_A_periph(AT91_PIN_PD9, 0); /* CFCE2 */
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+ at91_set_A_periph(AT91_PIN_PD14, 0); /* CFNRW */
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+
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+ pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "pata_at91" : "at91_cf";
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+ platform_device_register(pdev);
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+}
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+#else
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+void __init at91_add_device_cf(struct at91_cf_data *data) {}
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+#endif
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+
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+/* --------------------------------------------------------------------
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+ * NAND / SmartMedia
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+ * -------------------------------------------------------------------- */
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+
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+#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
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+static struct atmel_nand_data nand_data;
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+
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+#define NAND_BASE AT91_CHIPSELECT_3
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+
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+static struct resource nand_resources[] = {
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+ [0] = {
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+ .start = NAND_BASE,
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+ .end = NAND_BASE + SZ_256M - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ [1] = {
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+ .start = AT91SAM9263_BASE_ECC0,
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+ .end = AT91SAM9263_BASE_ECC0 + SZ_512 - 1,
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+ .flags = IORESOURCE_MEM,
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+ }
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+};
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+
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+static struct platform_device at91sam9263_nand_device = {
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+ .name = "atmel_nand",
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+ .id = -1,
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+ .dev = {
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+ .platform_data = &nand_data,
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+ },
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+ .resource = nand_resources,
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+ .num_resources = ARRAY_SIZE(nand_resources),
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+};
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+
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+void __init at91_add_device_nand(struct atmel_nand_data *data)
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+{
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+ unsigned long csa;
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+
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+ if (!data)
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+ return;
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+
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+ csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
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+ at91_matrix_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
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+
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+ /* enable pin */
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+ if (gpio_is_valid(data->enable_pin))
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+ at91_set_gpio_output(data->enable_pin, 1);
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+
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+ /* ready/busy pin */
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+ if (gpio_is_valid(data->rdy_pin))
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+ at91_set_gpio_input(data->rdy_pin, 1);
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+
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+ /* card detect pin */
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+ if (gpio_is_valid(data->det_pin))
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+ at91_set_gpio_input(data->det_pin, 1);
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+
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+ nand_data = *data;
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+ platform_device_register(&at91sam9263_nand_device);
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+}
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+#else
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+void __init at91_add_device_nand(struct atmel_nand_data *data) {}
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+#endif
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+
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+
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+/* --------------------------------------------------------------------
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+ * TWI (i2c)
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+ * -------------------------------------------------------------------- */
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+
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+/*
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+ * Prefer the GPIO code since the TWI controller isn't robust
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+ * (gets overruns and underruns under load) and can only issue
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+ * repeated STARTs in one scenario (the driver doesn't yet handle them).
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+ */
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+#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
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+
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+static struct i2c_gpio_platform_data pdata = {
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+ .sda_pin = AT91_PIN_PB4,
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+ .sda_is_open_drain = 1,
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+ .scl_pin = AT91_PIN_PB5,
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+ .scl_is_open_drain = 1,
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+ .udelay = 2, /* ~100 kHz */
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+};
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+
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+static struct platform_device at91sam9263_twi_device = {
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+ .name = "i2c-gpio",
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+ .id = 0,
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+ .dev.platform_data = &pdata,
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+};
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+
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+void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
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+{
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+ at91_set_GPIO_periph(AT91_PIN_PB4, 1); /* TWD (SDA) */
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+ at91_set_multi_drive(AT91_PIN_PB4, 1);
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+
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+ at91_set_GPIO_periph(AT91_PIN_PB5, 1); /* TWCK (SCL) */
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+ at91_set_multi_drive(AT91_PIN_PB5, 1);
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+
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+ i2c_register_board_info(0, devices, nr_devices);
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+ platform_device_register(&at91sam9263_twi_device);
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+}
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+
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+#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
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+
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+static struct resource twi_resources[] = {
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+ [0] = {
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+ .start = AT91SAM9263_BASE_TWI,
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+ .end = AT91SAM9263_BASE_TWI + SZ_16K - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ [1] = {
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+ .start = NR_IRQS_LEGACY + AT91SAM9263_ID_TWI,
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+ .end = NR_IRQS_LEGACY + AT91SAM9263_ID_TWI,
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+ .flags = IORESOURCE_IRQ,
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+ },
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+};
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+
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+static struct platform_device at91sam9263_twi_device = {
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+ .name = "i2c-at91sam9260",
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+ .id = 0,
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+ .resource = twi_resources,
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+ .num_resources = ARRAY_SIZE(twi_resources),
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+};
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+
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+void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
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+{
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+ /* pins used for TWI interface */
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+ at91_set_A_periph(AT91_PIN_PB4, 0); /* TWD */
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+ at91_set_multi_drive(AT91_PIN_PB4, 1);
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+
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+ at91_set_A_periph(AT91_PIN_PB5, 0); /* TWCK */
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