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@@ -1765,3 +1765,67 @@
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#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \
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(((Line) - 1) << FShft (LCCR2_LPP))
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#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */
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+ /* Width - 1 [Tln] (L_FCLK) */
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+#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \
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+ /* Width [1..64 Tln] */ \
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+ (((Tln) - 1) << FShft (LCCR2_VSW))
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+#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
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+ /* count [Tln] */
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+#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
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+ /* [0..255 Tln] */ \
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+ ((Tln) << FShft (LCCR2_EFW))
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+#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
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+ /* Wait count [Tln] */
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+#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
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+ /* [0..255 Tln] */ \
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+ ((Tln) << FShft (LCCR2_BFW))
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+
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+#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */
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+ /* [1..255] (L_PCLK) */
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+ /* fpix = fcpu/(2*(PCD + 2)) */
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+ /* Tpix = 2*(PCD + 2)*Tcpu */
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+#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \
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+ (((Div) - 4)/2 << FShft (LCCR3_PCD))
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+ /* fpix = fcpu/(2*Floor (Div/2)) */
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+ /* Tpix = 2*Floor (Div/2)*Tcpu */
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+#define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \
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+ (((Div) - 3)/2 << FShft (LCCR3_PCD))
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+ /* fpix = fcpu/(2*Ceil (Div/2)) */
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+ /* Tpix = 2*Ceil (Div/2)*Tcpu */
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+#define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */
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+ /* [Tln] (L_BIAS) */
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+#define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \
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+ (((Div) - 2)/2 << FShft (LCCR3_ACB))
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+ /* fac = fln/(2*Floor (Div/2)) */
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+ /* Tac = 2*Floor (Div/2)*Tln */
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+#define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \
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+ (((Div) - 1)/2 << FShft (LCCR3_ACB))
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+ /* fac = fln/(2*Ceil (Div/2)) */
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+ /* Tac = 2*Ceil (Div/2)*Tln */
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+#define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */
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+ /* Interrupt */
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+#define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \
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+ /* Off */ \
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+ (0 << FShft (LCCR3_API))
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+#define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \
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+ /* [1..15] */ \
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+ ((Trans) << FShft (LCCR3_API))
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+#define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */
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+ /* Polarity (L_FCLK) */
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+#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */
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+ /* active High */
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+#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
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+ /* active Low */
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+#define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */
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+ /* pulse Polarity (L_LCLK) */
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+#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */
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+ /* pulse active High */
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+#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */
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+ /* pulse active Low */
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+#define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */
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+#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
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+#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
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+#define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */
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+ /* active display mode) */
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+#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
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+#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */
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沈瑞清