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+/*
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+ * AM33XX Clock data
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+ *
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+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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+ * Vaibhav Hiremath <hvaibhav@ti.com>
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation version 2.
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+ *
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+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
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+ * kind, whether express or implied; without even the implied warranty
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+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/list.h>
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+#include <linux/clk-private.h>
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+#include <linux/clkdev.h>
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+#include <linux/io.h>
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+
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+#include "am33xx.h"
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+#include "soc.h"
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+#include "iomap.h"
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+#include "clock.h"
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+#include "control.h"
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+#include "cm.h"
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+#include "cm33xx.h"
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+#include "cm-regbits-33xx.h"
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+#include "prm.h"
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+
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+/* Modulemode control */
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+#define AM33XX_MODULEMODE_HWCTRL_SHIFT 0
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+#define AM33XX_MODULEMODE_SWCTRL_SHIFT 1
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+
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+/*LIST_HEAD(clocks);*/
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+
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+/* Root clocks */
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+
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+/* RTC 32k */
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+DEFINE_CLK_FIXED_RATE(clk_32768_ck, CLK_IS_ROOT, 32768, 0x0);
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+
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+/* On-Chip 32KHz RC OSC */
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+DEFINE_CLK_FIXED_RATE(clk_rc32k_ck, CLK_IS_ROOT, 32000, 0x0);
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+
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+/* Crystal input clks */
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+DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
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+
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+DEFINE_CLK_FIXED_RATE(virt_24000000_ck, CLK_IS_ROOT, 24000000, 0x0);
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+
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+DEFINE_CLK_FIXED_RATE(virt_25000000_ck, CLK_IS_ROOT, 25000000, 0x0);
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+
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+DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
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+
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+/* Oscillator clock */
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+/* 19.2, 24, 25 or 26 MHz */
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+static const char *sys_clkin_ck_parents[] = {
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+ "virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck",
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+ "virt_26000000_ck",
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+};
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+
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+/*
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+ * sys_clk in: input to the dpll and also used as funtional clock for,
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+ * adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
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+ *
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+ */
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+DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
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+ AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
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+ AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT,
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+ AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH,
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+ 0, NULL);
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+
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+/* External clock - 12 MHz */
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+DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 12000000, 0x0);
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+
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+/* Module clocks and DPLL outputs */
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+
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+/* DPLL_CORE */
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+static struct dpll_data dpll_core_dd = {
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+ .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE,
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+ .clk_bypass = &sys_clkin_ck,
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+ .clk_ref = &sys_clkin_ck,
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+ .control_reg = AM33XX_CM_CLKMODE_DPLL_CORE,
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+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
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+ .idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE,
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+ .mult_mask = AM33XX_DPLL_MULT_MASK,
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+ .div1_mask = AM33XX_DPLL_DIV_MASK,
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+ .enable_mask = AM33XX_DPLL_EN_MASK,
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+ .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
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+ .max_multiplier = 2047,
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+ .max_divider = 128,
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+ .min_divider = 1,
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+};
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+
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+/* CLKDCOLDO output */
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+static const char *dpll_core_ck_parents[] = {
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+ "sys_clkin_ck",
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袁明明