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@@ -1297,3 +1297,174 @@
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#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
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#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
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#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
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+#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
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+#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
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+#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
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+#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
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+#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
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+#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
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+#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
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+#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
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+#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
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+#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
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+#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
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+#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
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+#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
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+#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
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+#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
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+#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
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+#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
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+#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
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+#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
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+#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
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+#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
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+#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
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+#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
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+#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
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+#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
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+#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
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+#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
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+#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
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+#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
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+#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
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+#define EBUFE 0x02000000 /* Enable External Buffering Timing */
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+#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
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+#define EMREN 0x10000000 /* Extended Mode Register Enable */
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+#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
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+#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
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+
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+/* EBIU_SDBCTL Masks */
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+#define EBE 0x0001 /* Enable SDRAM External Bank */
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+#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
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+#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
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+#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
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+#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
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+#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
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+#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
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+#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
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+#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
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+#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
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+#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
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+
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+/* EBIU_SDSTAT Masks */
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+#define SDCI 0x0001 /* SDRAM Controller Idle */
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+#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
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+#define SDPUA 0x0004 /* SDRAM Power-Up Active */
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+#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
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+#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
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+#define BGSTAT 0x0020 /* Bus Grant Status */
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+
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+/* ************************** DMA CONTROLLER MASKS ********************************/
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+
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+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
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+#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
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+#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
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+#define PMAP_PPI 0x0000 /* PPI Port DMA */
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+#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
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+#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
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+#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
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+#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
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+#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
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+#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
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+#define PMAP_SPI 0x7000 /* SPI Port DMA */
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+#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
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+#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
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+#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
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+#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
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+
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+/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
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+/* PPI_CONTROL Masks */
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+#define PORT_EN 0x0001 /* PPI Port Enable */
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+#define PORT_DIR 0x0002 /* PPI Port Direction */
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+#define XFR_TYPE 0x000C /* PPI Transfer Type */
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+#define PORT_CFG 0x0030 /* PPI Port Configuration */
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+#define FLD_SEL 0x0040 /* PPI Active Field Select */
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+#define PACK_EN 0x0080 /* PPI Packing Mode */
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+#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
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+#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
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+#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
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+#define DLENGTH 0x3800 /* PPI Data Length */
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+#define DLEN_8 0x0000 /* Data Length = 8 Bits */
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+#define DLEN_10 0x0800 /* Data Length = 10 Bits */
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+#define DLEN_11 0x1000 /* Data Length = 11 Bits */
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+#define DLEN_12 0x1800 /* Data Length = 12 Bits */
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+#define DLEN_13 0x2000 /* Data Length = 13 Bits */
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+#define DLEN_14 0x2800 /* Data Length = 14 Bits */
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+#define DLEN_15 0x3000 /* Data Length = 15 Bits */
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+#define DLEN_16 0x3800 /* Data Length = 16 Bits */
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+#define POLC 0x4000 /* PPI Clock Polarity */
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+#define POLS 0x8000 /* PPI Frame Sync Polarity */
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+
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+/* PPI_STATUS Masks */
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+#define FLD 0x0400 /* Field Indicator */
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+#define FT_ERR 0x0800 /* Frame Track Error */
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+#define OVR 0x1000 /* FIFO Overflow Error */
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+#define UNDR 0x2000 /* FIFO Underrun Error */
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+#define ERR_DET 0x4000 /* Error Detected Indicator */
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+#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
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+
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+
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+/* ******************* PIN CONTROL REGISTER MASKS ************************/
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+/* PORT_MUX Masks */
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+#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
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+#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
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+#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
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+
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+#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
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+#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
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+#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
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+#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
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+
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+#define PFDE 0x0008 /* Port F DMA Request Enable */
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+#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
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+#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
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+
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+#define PFTE 0x0010 /* Port F Timer Enable */
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+#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
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+#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
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+
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+#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
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+#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
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+#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
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+
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+#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
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+#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
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+#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
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+
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+#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
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+#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
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+#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
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+
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+#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
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+#define PFFE_TIMER 0x0000 /* Enable TMR2 */
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+#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
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+
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+#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
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+#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
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+#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
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+
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+#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
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+#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
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+#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
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+
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+#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
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+#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
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+#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
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+
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+/* entry addresses of the user-callable Boot ROM functions */
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+
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+#define _BOOTROM_RESET 0xEF000000
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+#define _BOOTROM_FINAL_INIT 0xEF000002
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+#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
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+#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
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+#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
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+#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
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+#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
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+#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
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+#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
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+
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+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
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+#define PGDE_UART PFDE_UART
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+#define PGDE_DMA PFDE_DMA
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+#define CKELOW SCKELOW
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+#endif /* _DEF_BF534_H */
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