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@@ -334,3 +334,87 @@ void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size)
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* Should be reverted after this issue is root caused.
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*/
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while (!(DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE))
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+ continue;
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+#endif
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+}
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+
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+void __init early_dma_memcpy_done(void)
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+{
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+ early_shadow_stamp();
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+
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+ while ((bfin_read_MDMA_S0_CONFIG() && !(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) ||
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+ (bfin_read_MDMA_S1_CONFIG() && !(bfin_read_MDMA_D1_IRQ_STATUS() & DMA_DONE)))
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+ continue;
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+
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+ bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
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+ bfin_write_MDMA_D1_IRQ_STATUS(DMA_DONE | DMA_ERR);
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+ /*
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+ * Now that DMA is done, we would normally flush cache, but
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+ * i/d cache isn't running this early, so we don't bother,
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+ * and just clear out the DMA channel for next time
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+ */
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+ bfin_write_MDMA_S0_CONFIG(0);
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+ bfin_write_MDMA_S1_CONFIG(0);
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+ bfin_write_MDMA_D0_CONFIG(0);
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+ bfin_write_MDMA_D1_CONFIG(0);
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+
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+ __builtin_bfin_ssync();
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+}
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+
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+#if defined(CH_MEM_STREAM3_SRC) && defined(CONFIG_BF60x)
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+#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S3_CONFIG
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+#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S3_CONFIG
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+#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S3_START_ADDR
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+#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S3_IRQ_STATUS
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+#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S3_X_COUNT
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+#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S3_X_MODIFY
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+#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S3_Y_COUNT
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+#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S3_Y_MODIFY
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+#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D3_CONFIG
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+#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D3_START_ADDR
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+#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D3_IRQ_STATUS
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+#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D3_IRQ_STATUS
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+#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D3_X_COUNT
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+#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D3_X_MODIFY
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+#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D3_Y_COUNT
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+#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D3_Y_MODIFY
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+#else
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+#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S0_CONFIG
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+#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S0_CONFIG
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+#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S0_START_ADDR
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+#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S0_IRQ_STATUS
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+#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S0_X_COUNT
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+#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S0_X_MODIFY
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+#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S0_Y_COUNT
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+#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S0_Y_MODIFY
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+#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D0_CONFIG
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+#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D0_START_ADDR
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+#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D0_IRQ_STATUS
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+#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D0_IRQ_STATUS
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+#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D0_X_COUNT
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+#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D0_X_MODIFY
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+#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D0_Y_COUNT
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+#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D0_Y_MODIFY
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+#endif
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+
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+/**
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+ * __dma_memcpy - program the MDMA registers
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+ *
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+ * Actually program MDMA0 and wait for the transfer to finish. Disable IRQs
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+ * while programming registers so that everything is fully configured. Wait
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+ * for DMA to finish with IRQs enabled. If interrupted, the initial DMA_DONE
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+ * check will make sure we don't clobber any existing transfer.
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+ */
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+static void __dma_memcpy(u32 daddr, s16 dmod, u32 saddr, s16 smod, size_t cnt, u32 conf)
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+{
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+ static DEFINE_SPINLOCK(mdma_lock);
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&mdma_lock, flags);
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+
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+ /* Force a sync in case a previous config reset on this channel
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+ * occurred. This is needed so subsequent writes to DMA registers
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+ * are not spuriously lost/corrupted. Do it under irq lock and
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+ * without the anomaly version (because we are atomic already).
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+ */
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+ __builtin_bfin_ssync();
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