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@@ -86,3 +86,87 @@ extern void __iomem *mx3_ccm_base;
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#define MXC_CCM_CCMR_MPE (1 << 3)
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#define MXC_CCM_CCMR_PRCS_OFFSET 1
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#define MXC_CCM_CCMR_PRCS_MASK (0x3 << 1)
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+
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+#define MXC_CCM_PDR0_CSI_PODF_OFFSET 26
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+#define MXC_CCM_PDR0_CSI_PODF_MASK (0x3F << 26)
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+#define MXC_CCM_PDR0_CSI_PRDF_OFFSET 23
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+#define MXC_CCM_PDR0_CSI_PRDF_MASK (0x7 << 23)
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+#define MXC_CCM_PDR0_PER_PODF_OFFSET 16
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+#define MXC_CCM_PDR0_PER_PODF_MASK (0x1F << 16)
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+#define MXC_CCM_PDR0_HSP_PODF_OFFSET 11
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+#define MXC_CCM_PDR0_HSP_PODF_MASK (0x7 << 11)
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+#define MXC_CCM_PDR0_NFC_PODF_OFFSET 8
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+#define MXC_CCM_PDR0_NFC_PODF_MASK (0x7 << 8)
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+#define MXC_CCM_PDR0_IPG_PODF_OFFSET 6
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+#define MXC_CCM_PDR0_IPG_PODF_MASK (0x3 << 6)
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+#define MXC_CCM_PDR0_MAX_PODF_OFFSET 3
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+#define MXC_CCM_PDR0_MAX_PODF_MASK (0x7 << 3)
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+#define MXC_CCM_PDR0_MCU_PODF_OFFSET 0
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+#define MXC_CCM_PDR0_MCU_PODF_MASK 0x7
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+
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+#define MXC_CCM_PDR1_USB_PRDF_OFFSET 30
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+#define MXC_CCM_PDR1_USB_PRDF_MASK (0x3 << 30)
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+#define MXC_CCM_PDR1_USB_PODF_OFFSET 27
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+#define MXC_CCM_PDR1_USB_PODF_MASK (0x7 << 27)
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+#define MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET 24
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+#define MXC_CCM_PDR1_FIRI_PRE_PODF_MASK (0x7 << 24)
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+#define MXC_CCM_PDR1_FIRI_PODF_OFFSET 18
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+#define MXC_CCM_PDR1_FIRI_PODF_MASK (0x3F << 18)
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+#define MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET 15
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+#define MXC_CCM_PDR1_SSI2_PRE_PODF_MASK (0x7 << 15)
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+#define MXC_CCM_PDR1_SSI2_PODF_OFFSET 9
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+#define MXC_CCM_PDR1_SSI2_PODF_MASK (0x3F << 9)
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+#define MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET 6
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+#define MXC_CCM_PDR1_SSI1_PRE_PODF_MASK (0x7 << 6)
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+#define MXC_CCM_PDR1_SSI1_PODF_OFFSET 0
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+#define MXC_CCM_PDR1_SSI1_PODF_MASK 0x3F
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+
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+/* Bit definitions for RCSR */
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+#define MXC_CCM_RCSR_NF16B 0x80000000
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+
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+/*
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+ * LTR0 register offsets
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+ */
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+#define MXC_CCM_LTR0_DIV3CK_OFFSET 1
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+#define MXC_CCM_LTR0_DIV3CK_MASK (0x3 << 1)
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+#define MXC_CCM_LTR0_DNTHR_OFFSET 16
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+#define MXC_CCM_LTR0_DNTHR_MASK (0x3F << 16)
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+#define MXC_CCM_LTR0_UPTHR_OFFSET 22
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+#define MXC_CCM_LTR0_UPTHR_MASK (0x3F << 22)
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+
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+/*
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+ * LTR1 register offsets
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+ */
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+#define MXC_CCM_LTR1_PNCTHR_OFFSET 0
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+#define MXC_CCM_LTR1_PNCTHR_MASK 0x3F
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+#define MXC_CCM_LTR1_UPCNT_OFFSET 6
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+#define MXC_CCM_LTR1_UPCNT_MASK (0xFF << 6)
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+#define MXC_CCM_LTR1_DNCNT_OFFSET 14
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+#define MXC_CCM_LTR1_DNCNT_MASK (0xFF << 14)
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+#define MXC_CCM_LTR1_LTBRSR_MASK 0x400000
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+#define MXC_CCM_LTR1_LTBRSR_OFFSET 22
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+#define MXC_CCM_LTR1_LTBRSR 0x400000
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+#define MXC_CCM_LTR1_LTBRSH 0x800000
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+
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+/*
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+ * LTR2 bit definitions. x ranges from 0 for WSW9 to 6 for WSW15
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+ */
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+#define MXC_CCM_LTR2_WSW_OFFSET(x) (11 + (x) * 3)
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+#define MXC_CCM_LTR2_WSW_MASK(x) (0x7 << \
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+ MXC_CCM_LTR2_WSW_OFFSET((x)))
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+#define MXC_CCM_LTR2_EMAC_OFFSET 0
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+#define MXC_CCM_LTR2_EMAC_MASK 0x1FF
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+
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+/*
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+ * LTR3 bit definitions. x ranges from 0 for WSW0 to 8 for WSW8
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+ */
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+#define MXC_CCM_LTR3_WSW_OFFSET(x) (5 + (x) * 3)
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+#define MXC_CCM_LTR3_WSW_MASK(x) (0x7 << \
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+ MXC_CCM_LTR3_WSW_OFFSET((x)))
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+
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+#define MXC_CCM_PMCR0_DFSUP1 0x80000000
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+#define MXC_CCM_PMCR0_DFSUP1_SPLL (0 << 31)
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+#define MXC_CCM_PMCR0_DFSUP1_MPLL (1 << 31)
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+#define MXC_CCM_PMCR0_DFSUP0 0x40000000
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+#define MXC_CCM_PMCR0_DFSUP0_PLL (0 << 30)
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+#define MXC_CCM_PMCR0_DFSUP0_PDR (1 << 30)
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吉超博