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@@ -0,0 +1,112 @@
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+/*
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+ * Copyright 2005-2010 Analog Devices Inc.
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+ *
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+ * Licensed under the GPL-2 or later
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+ */
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+
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+#ifndef _CDEF_BF534_H
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+#define _CDEF_BF534_H
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+
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+/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
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+#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
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+#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
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+#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
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+#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
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+#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
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+#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
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+#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
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+#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
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+#define bfin_read_CHIPID() bfin_read32(CHIPID)
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+
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+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
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+#define bfin_read_SWRST() bfin_read16(SWRST)
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+#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
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+#define bfin_read_SYSCR() bfin_read16(SYSCR)
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+#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
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+#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
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+#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT,val)
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+#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
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+#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val)
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+#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
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+#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
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+#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
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+#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
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+#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
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+#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
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+#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
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+#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
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+#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
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+#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val)
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+#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
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+#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val)
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+
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+/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
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+#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
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+#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val)
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+#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
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+#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val)
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+#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
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+#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val)
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+
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+/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
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+#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
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+#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val)
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+#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
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+#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val)
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+#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
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+#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val)
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+#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
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+#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val)
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+#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
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+#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val)
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+#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
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+#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val)
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+#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
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+#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
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+
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+/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
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+#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
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+#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR,val)
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+#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
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+#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR,val)
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+#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
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+#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL,val)
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+#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
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+#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER,val)
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+#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
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+#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH,val)
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+#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
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+#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR,val)
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+#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
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+#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR,val)
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+#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
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+#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR,val)
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+#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
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+#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR,val)
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+#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
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+#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR,val)
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+#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
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+#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR,val)
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+#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
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+#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL,val)
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+
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+/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
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+#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
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+#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
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+#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
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+#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
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+#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
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+#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
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+#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
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+#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
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+#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
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+#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
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+#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
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+#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
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+#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
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+#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
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+
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+/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
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+#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
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+#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
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+#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
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