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@@ -95,3 +95,161 @@
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#define APECS_IOC_HAXR2 (IDENT_ADDR + 0x1A00001C0UL)
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#define APECS_IOC_PMLT (IDENT_ADDR + 0x1A00001E0UL)
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+
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+#define APECS_IOC_TLBTAG0 (IDENT_ADDR + 0x1A0000200UL)
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+#define APECS_IOC_TLBTAG1 (IDENT_ADDR + 0x1A0000220UL)
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+#define APECS_IOC_TLBTAG2 (IDENT_ADDR + 0x1A0000240UL)
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+#define APECS_IOC_TLBTAG3 (IDENT_ADDR + 0x1A0000260UL)
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+#define APECS_IOC_TLBTAG4 (IDENT_ADDR + 0x1A0000280UL)
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+#define APECS_IOC_TLBTAG5 (IDENT_ADDR + 0x1A00002A0UL)
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+#define APECS_IOC_TLBTAG6 (IDENT_ADDR + 0x1A00002C0UL)
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+#define APECS_IOC_TLBTAG7 (IDENT_ADDR + 0x1A00002E0UL)
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+
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+#define APECS_IOC_TLBDATA0 (IDENT_ADDR + 0x1A0000300UL)
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+#define APECS_IOC_TLBDATA1 (IDENT_ADDR + 0x1A0000320UL)
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+#define APECS_IOC_TLBDATA2 (IDENT_ADDR + 0x1A0000340UL)
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+#define APECS_IOC_TLBDATA3 (IDENT_ADDR + 0x1A0000360UL)
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+#define APECS_IOC_TLBDATA4 (IDENT_ADDR + 0x1A0000380UL)
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+#define APECS_IOC_TLBDATA5 (IDENT_ADDR + 0x1A00003A0UL)
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+#define APECS_IOC_TLBDATA6 (IDENT_ADDR + 0x1A00003C0UL)
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+#define APECS_IOC_TLBDATA7 (IDENT_ADDR + 0x1A00003E0UL)
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+
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+#define APECS_IOC_TBIA (IDENT_ADDR + 0x1A0000400UL)
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+
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+
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+/*
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+ * 21071-CA Control and Status registers.
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+ * These are used to program memory timing,
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+ * configure memory and initialise the B-Cache.
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+ */
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+#define APECS_MEM_GCR (IDENT_ADDR + 0x180000000UL)
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+#define APECS_MEM_EDSR (IDENT_ADDR + 0x180000040UL)
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+#define APECS_MEM_TAR (IDENT_ADDR + 0x180000060UL)
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+#define APECS_MEM_ELAR (IDENT_ADDR + 0x180000080UL)
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+#define APECS_MEM_EHAR (IDENT_ADDR + 0x1800000a0UL)
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+#define APECS_MEM_SFT_RST (IDENT_ADDR + 0x1800000c0UL)
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+#define APECS_MEM_LDxLAR (IDENT_ADDR + 0x1800000e0UL)
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+#define APECS_MEM_LDxHAR (IDENT_ADDR + 0x180000100UL)
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+#define APECS_MEM_GTR (IDENT_ADDR + 0x180000200UL)
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+#define APECS_MEM_RTR (IDENT_ADDR + 0x180000220UL)
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+#define APECS_MEM_VFPR (IDENT_ADDR + 0x180000240UL)
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+#define APECS_MEM_PDLDR (IDENT_ADDR + 0x180000260UL)
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+#define APECS_MEM_PDhDR (IDENT_ADDR + 0x180000280UL)
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+
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+/* Bank x Base Address Register */
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+#define APECS_MEM_B0BAR (IDENT_ADDR + 0x180000800UL)
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+#define APECS_MEM_B1BAR (IDENT_ADDR + 0x180000820UL)
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+#define APECS_MEM_B2BAR (IDENT_ADDR + 0x180000840UL)
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+#define APECS_MEM_B3BAR (IDENT_ADDR + 0x180000860UL)
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+#define APECS_MEM_B4BAR (IDENT_ADDR + 0x180000880UL)
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+#define APECS_MEM_B5BAR (IDENT_ADDR + 0x1800008A0UL)
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+#define APECS_MEM_B6BAR (IDENT_ADDR + 0x1800008C0UL)
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+#define APECS_MEM_B7BAR (IDENT_ADDR + 0x1800008E0UL)
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+#define APECS_MEM_B8BAR (IDENT_ADDR + 0x180000900UL)
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+
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+/* Bank x Configuration Register */
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+#define APECS_MEM_B0BCR (IDENT_ADDR + 0x180000A00UL)
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+#define APECS_MEM_B1BCR (IDENT_ADDR + 0x180000A20UL)
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+#define APECS_MEM_B2BCR (IDENT_ADDR + 0x180000A40UL)
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+#define APECS_MEM_B3BCR (IDENT_ADDR + 0x180000A60UL)
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+#define APECS_MEM_B4BCR (IDENT_ADDR + 0x180000A80UL)
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+#define APECS_MEM_B5BCR (IDENT_ADDR + 0x180000AA0UL)
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+#define APECS_MEM_B6BCR (IDENT_ADDR + 0x180000AC0UL)
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+#define APECS_MEM_B7BCR (IDENT_ADDR + 0x180000AE0UL)
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+#define APECS_MEM_B8BCR (IDENT_ADDR + 0x180000B00UL)
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+
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+/* Bank x Timing Register A */
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+#define APECS_MEM_B0TRA (IDENT_ADDR + 0x180000C00UL)
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+#define APECS_MEM_B1TRA (IDENT_ADDR + 0x180000C20UL)
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+#define APECS_MEM_B2TRA (IDENT_ADDR + 0x180000C40UL)
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+#define APECS_MEM_B3TRA (IDENT_ADDR + 0x180000C60UL)
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+#define APECS_MEM_B4TRA (IDENT_ADDR + 0x180000C80UL)
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+#define APECS_MEM_B5TRA (IDENT_ADDR + 0x180000CA0UL)
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+#define APECS_MEM_B6TRA (IDENT_ADDR + 0x180000CC0UL)
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+#define APECS_MEM_B7TRA (IDENT_ADDR + 0x180000CE0UL)
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+#define APECS_MEM_B8TRA (IDENT_ADDR + 0x180000D00UL)
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+
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+/* Bank x Timing Register B */
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+#define APECS_MEM_B0TRB (IDENT_ADDR + 0x180000E00UL)
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+#define APECS_MEM_B1TRB (IDENT_ADDR + 0x180000E20UL)
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+#define APECS_MEM_B2TRB (IDENT_ADDR + 0x180000E40UL)
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+#define APECS_MEM_B3TRB (IDENT_ADDR + 0x180000E60UL)
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+#define APECS_MEM_B4TRB (IDENT_ADDR + 0x180000E80UL)
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+#define APECS_MEM_B5TRB (IDENT_ADDR + 0x180000EA0UL)
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+#define APECS_MEM_B6TRB (IDENT_ADDR + 0x180000EC0UL)
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+#define APECS_MEM_B7TRB (IDENT_ADDR + 0x180000EE0UL)
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+#define APECS_MEM_B8TRB (IDENT_ADDR + 0x180000F00UL)
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+
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+
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+/*
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+ * Memory spaces:
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+ */
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+#define APECS_IACK_SC (IDENT_ADDR + 0x1b0000000UL)
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+#define APECS_CONF (IDENT_ADDR + 0x1e0000000UL)
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+#define APECS_IO (IDENT_ADDR + 0x1c0000000UL)
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+#define APECS_SPARSE_MEM (IDENT_ADDR + 0x200000000UL)
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+#define APECS_DENSE_MEM (IDENT_ADDR + 0x300000000UL)
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+
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+
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+/*
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+ * Bit definitions for I/O Controller status register 0:
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+ */
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+#define APECS_IOC_STAT0_CMD 0xf
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+#define APECS_IOC_STAT0_ERR (1<<4)
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+#define APECS_IOC_STAT0_LOST (1<<5)
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+#define APECS_IOC_STAT0_THIT (1<<6)
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+#define APECS_IOC_STAT0_TREF (1<<7)
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+#define APECS_IOC_STAT0_CODE_SHIFT 8
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+#define APECS_IOC_STAT0_CODE_MASK 0x7
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+#define APECS_IOC_STAT0_P_NBR_SHIFT 13
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+#define APECS_IOC_STAT0_P_NBR_MASK 0x7ffff
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+
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+#define APECS_HAE_ADDRESS APECS_IOC_HAXR1
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+
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+
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+/*
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+ * Data structure for handling APECS machine checks:
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+ */
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+
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+struct el_apecs_mikasa_sysdata_mcheck
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+{
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+ unsigned long coma_gcr;
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+ unsigned long coma_edsr;
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+ unsigned long coma_ter;
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+ unsigned long coma_elar;
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+ unsigned long coma_ehar;
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+ unsigned long coma_ldlr;
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+ unsigned long coma_ldhr;
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+ unsigned long coma_base0;
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+ unsigned long coma_base1;
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+ unsigned long coma_base2;
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+ unsigned long coma_base3;
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+ unsigned long coma_cnfg0;
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+ unsigned long coma_cnfg1;
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+ unsigned long coma_cnfg2;
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+ unsigned long coma_cnfg3;
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+ unsigned long epic_dcsr;
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+ unsigned long epic_pear;
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+ unsigned long epic_sear;
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+ unsigned long epic_tbr1;
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+ unsigned long epic_tbr2;
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+ unsigned long epic_pbr1;
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+ unsigned long epic_pbr2;
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+ unsigned long epic_pmr1;
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+ unsigned long epic_pmr2;
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+ unsigned long epic_harx1;
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+ unsigned long epic_harx2;
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+ unsigned long epic_pmlt;
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+ unsigned long epic_tag0;
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+ unsigned long epic_tag1;
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+ unsigned long epic_tag2;
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+ unsigned long epic_tag3;
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+ unsigned long epic_tag4;
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+ unsigned long epic_tag5;
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+ unsigned long epic_tag6;
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+ unsigned long epic_tag7;
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+ unsigned long epic_data0;
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+ unsigned long epic_data1;
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+ unsigned long epic_data2;
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+ unsigned long epic_data3;
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+ unsigned long epic_data4;
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张婷