|
@@ -0,0 +1,125 @@
|
|
|
+/*
|
|
|
+ * OMAP44xx MUX registers and bitfields
|
|
|
+ *
|
|
|
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
|
|
|
+ *
|
|
|
+ * Benoit Cousson (b-cousson@ti.com)
|
|
|
+ *
|
|
|
+ * This file is automatically generated from the OMAP hardware databases.
|
|
|
+ * We respectfully ask that any modifications to this file be coordinated
|
|
|
+ * with the public linux-omap@vger.kernel.org mailing list and the
|
|
|
+ * authors above to ensure that the autogeneration scripts are kept
|
|
|
+ * up-to-date with the file contents.
|
|
|
+ *
|
|
|
+ * This program is free software; you can redistribute it and/or modify
|
|
|
+ * it under the terms of the GNU General Public License version 2 as
|
|
|
+ * published by the Free Software Foundation.
|
|
|
+ */
|
|
|
+
|
|
|
+#ifndef __ARCH_ARM_MACH_OMAP2_MUX_44XX_H
|
|
|
+#define __ARCH_ARM_MACH_OMAP2_MUX_44XX_H
|
|
|
+
|
|
|
+#define OMAP4_MUX(M0, mux_value) \
|
|
|
+{ \
|
|
|
+ .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
|
|
|
+ .value = (mux_value), \
|
|
|
+}
|
|
|
+
|
|
|
+/* ctrl_module_pad_core base address */
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE 0x4a100000
|
|
|
+
|
|
|
+/* ctrl_module_pad_core registers offset */
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET 0x0040
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD1_OFFSET 0x0042
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD2_OFFSET 0x0044
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD3_OFFSET 0x0046
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD4_OFFSET 0x0048
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD5_OFFSET 0x004a
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD6_OFFSET 0x004c
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD7_OFFSET 0x004e
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD8_OFFSET 0x0050
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD9_OFFSET 0x0052
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD10_OFFSET 0x0054
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD11_OFFSET 0x0056
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD12_OFFSET 0x0058
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD13_OFFSET 0x005a
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD14_OFFSET 0x005c
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD15_OFFSET 0x005e
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A16_OFFSET 0x0060
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A17_OFFSET 0x0062
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A18_OFFSET 0x0064
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A19_OFFSET 0x0066
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A20_OFFSET 0x0068
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A21_OFFSET 0x006a
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A22_OFFSET 0x006c
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A23_OFFSET 0x006e
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A24_OFFSET 0x0070
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A25_OFFSET 0x0072
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS0_OFFSET 0x0074
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS1_OFFSET 0x0076
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS2_OFFSET 0x0078
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS3_OFFSET 0x007a
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NWP_OFFSET 0x007c
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_CLK_OFFSET 0x007e
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NADV_ALE_OFFSET 0x0080
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NOE_OFFSET 0x0082
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NWE_OFFSET 0x0084
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE0_CLE_OFFSET 0x0086
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE1_OFFSET 0x0088
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT0_OFFSET 0x008a
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT1_OFFSET 0x008c
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA11_OFFSET 0x008e
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA12_OFFSET 0x0090
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA13_OFFSET 0x0092
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA14_OFFSET 0x0094
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA15_OFFSET 0x0096
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_HDMI_HPD_OFFSET 0x0098
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_HDMI_CEC_OFFSET 0x009a
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SCL_OFFSET 0x009c
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SDA_OFFSET 0x009e
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX0_OFFSET 0x00a0
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY0_OFFSET 0x00a2
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX1_OFFSET 0x00a4
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY1_OFFSET 0x00a6
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX2_OFFSET 0x00a8
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY2_OFFSET 0x00aa
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX3_OFFSET 0x00ac
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY3_OFFSET 0x00ae
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX4_OFFSET 0x00b0
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY4_OFFSET 0x00b2
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_CSI22_DX0_OFFSET 0x00b4
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_CSI22_DY0_OFFSET 0x00b6
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_CSI22_DX1_OFFSET 0x00b8
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_CSI22_DY1_OFFSET 0x00ba
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_CAM_SHUTTER_OFFSET 0x00bc
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_CAM_STROBE_OFFSET 0x00be
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_CAM_GLOBALRESET_OFFSET 0x00c0
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_CLK_OFFSET 0x00c2
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_STP_OFFSET 0x00c4
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DIR_OFFSET 0x00c6
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_NXT_OFFSET 0x00c8
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT0_OFFSET 0x00ca
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT1_OFFSET 0x00cc
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT2_OFFSET 0x00ce
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT3_OFFSET 0x00d0
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT4_OFFSET 0x00d2
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT5_OFFSET 0x00d4
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT6_OFFSET 0x00d6
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT7_OFFSET 0x00d8
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_DATA_OFFSET 0x00da
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_STROBE_OFFSET 0x00dc
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DP_OFFSET 0x00de
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DM_OFFSET 0x00e0
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CLK_OFFSET 0x00e2
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CMD_OFFSET 0x00e4
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT0_OFFSET 0x00e6
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT1_OFFSET 0x00e8
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT2_OFFSET 0x00ea
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT3_OFFSET 0x00ec
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT4_OFFSET 0x00ee
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT5_OFFSET 0x00f0
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT6_OFFSET 0x00f2
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT7_OFFSET 0x00f4
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_CLKX_OFFSET 0x00f6
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DR_OFFSET 0x00f8
|
|
|
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DX_OFFSET 0x00fa
|