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@@ -0,0 +1,125 @@
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+/*
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+ * Copyright(c) 2006, Intel Corporation.
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms and conditions of the GNU General Public License,
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+ * version 2, as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope it will be useful, but WITHOUT
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+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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+ * more details.
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+ *
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+ * You should have received a copy of the GNU General Public License along with
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+ * this program; if not, write to the Free Software Foundation, Inc.,
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+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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+ *
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+ */
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+#ifndef _ADMA_H
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+#define _ADMA_H
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+#include <linux/types.h>
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+#include <linux/io.h>
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+#include <mach/hardware.h>
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+#include <asm/hardware/iop_adma.h>
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+
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+#define ADMA_ACCR(chan) (chan->mmr_base + 0x0)
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+#define ADMA_ACSR(chan) (chan->mmr_base + 0x4)
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+#define ADMA_ADAR(chan) (chan->mmr_base + 0x8)
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+#define ADMA_IIPCR(chan) (chan->mmr_base + 0x18)
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+#define ADMA_IIPAR(chan) (chan->mmr_base + 0x1c)
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+#define ADMA_IIPUAR(chan) (chan->mmr_base + 0x20)
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+#define ADMA_ANDAR(chan) (chan->mmr_base + 0x24)
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+#define ADMA_ADCR(chan) (chan->mmr_base + 0x28)
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+#define ADMA_CARMD(chan) (chan->mmr_base + 0x2c)
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+#define ADMA_ABCR(chan) (chan->mmr_base + 0x30)
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+#define ADMA_DLADR(chan) (chan->mmr_base + 0x34)
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+#define ADMA_DUADR(chan) (chan->mmr_base + 0x38)
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+#define ADMA_SLAR(src, chan) (chan->mmr_base + (0x3c + (src << 3)))
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+#define ADMA_SUAR(src, chan) (chan->mmr_base + (0x40 + (src << 3)))
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+
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+struct iop13xx_adma_src {
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+ u32 src_addr;
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+ union {
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+ u32 upper_src_addr;
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+ struct {
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+ unsigned int pq_upper_src_addr:24;
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+ unsigned int pq_dmlt:8;
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+ };
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+ };
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+};
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+
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+struct iop13xx_adma_desc_ctrl {
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+ unsigned int int_en:1;
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+ unsigned int xfer_dir:2;
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+ unsigned int src_select:4;
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+ unsigned int zero_result:1;
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+ unsigned int block_fill_en:1;
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+ unsigned int crc_gen_en:1;
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+ unsigned int crc_xfer_dis:1;
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+ unsigned int crc_seed_fetch_dis:1;
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+ unsigned int status_write_back_en:1;
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+ unsigned int endian_swap_en:1;
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+ unsigned int reserved0:2;
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+ unsigned int pq_update_xfer_en:1;
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+ unsigned int dual_xor_en:1;
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+ unsigned int pq_xfer_en:1;
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+ unsigned int p_xfer_dis:1;
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+ unsigned int reserved1:10;
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+ unsigned int relax_order_en:1;
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+ unsigned int no_snoop_en:1;
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+};
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+
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+struct iop13xx_adma_byte_count {
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+ unsigned int byte_count:24;
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+ unsigned int host_if:3;
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+ unsigned int reserved:2;
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+ unsigned int zero_result_err_q:1;
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+ unsigned int zero_result_err:1;
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+ unsigned int tx_complete:1;
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+};
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+
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+struct iop13xx_adma_desc_hw {
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+ u32 next_desc;
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+ union {
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+ u32 desc_ctrl;
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+ struct iop13xx_adma_desc_ctrl desc_ctrl_field;
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+ };
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+ union {
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+ u32 crc_addr;
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+ u32 block_fill_data;
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+ u32 q_dest_addr;
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+ };
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+ union {
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+ u32 byte_count;
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+ struct iop13xx_adma_byte_count byte_count_field;
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+ };
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+ union {
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+ u32 dest_addr;
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+ u32 p_dest_addr;
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+ };
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+ union {
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+ u32 upper_dest_addr;
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+ u32 pq_upper_dest_addr;
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+ };
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+ struct iop13xx_adma_src src[1];
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+};
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+
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+struct iop13xx_adma_desc_dual_xor {
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+ u32 next_desc;
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+ u32 desc_ctrl;
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+ u32 reserved;
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+ u32 byte_count;
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+ u32 h_dest_addr;
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+ u32 h_upper_dest_addr;
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+ u32 src0_addr;
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+ u32 upper_src0_addr;
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+ u32 src1_addr;
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+ u32 upper_src1_addr;
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+ u32 h_src_addr;
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+ u32 h_upper_src_addr;
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+ u32 d_src_addr;
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+ u32 d_upper_src_addr;
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+ u32 d_dest_addr;
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+ u32 d_upper_dest_addr;
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+};
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+
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