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@@ -63,3 +63,68 @@
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#define SHIFT_TYPE(i) (i & 0x60)
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#define SHIFT_TYPE(i) (i & 0x60)
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#define SHIFT_LSL 0x00
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#define SHIFT_LSL 0x00
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#define SHIFT_LSR 0x20
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#define SHIFT_LSR 0x20
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+#define SHIFT_ASR 0x40
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+#define SHIFT_RORRRX 0x60
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+
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+#define BAD_INSTR 0xdeadc0de
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+
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+/* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
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+#define IS_T32(hi16) \
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+ (((hi16) & 0xe000) == 0xe000 && ((hi16) & 0x1800))
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+
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+static unsigned long ai_user;
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+static unsigned long ai_sys;
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+static unsigned long ai_skipped;
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+static unsigned long ai_half;
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+static unsigned long ai_word;
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+static unsigned long ai_dword;
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+static unsigned long ai_multi;
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+static int ai_usermode;
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+
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+core_param(alignment, ai_usermode, int, 0600);
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+
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+#define UM_WARN (1 << 0)
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+#define UM_FIXUP (1 << 1)
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+#define UM_SIGNAL (1 << 2)
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+
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+/* Return true if and only if the ARMv6 unaligned access model is in use. */
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+static bool cpu_is_v6_unaligned(void)
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+{
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+ return cpu_architecture() >= CPU_ARCH_ARMv6 && (cr_alignment & CR_U);
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+}
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+
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+static int safe_usermode(int new_usermode, bool warn)
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+{
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+ /*
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+ * ARMv6 and later CPUs can perform unaligned accesses for
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+ * most single load and store instructions up to word size.
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+ * LDM, STM, LDRD and STRD still need to be handled.
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+ *
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+ * Ignoring the alignment fault is not an option on these
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+ * CPUs since we spin re-faulting the instruction without
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+ * making any progress.
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+ */
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+ if (cpu_is_v6_unaligned() && !(new_usermode & (UM_FIXUP | UM_SIGNAL))) {
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+ new_usermode |= UM_FIXUP;
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+
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+ if (warn)
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+ printk(KERN_WARNING "alignment: ignoring faults is unsafe on this CPU. Defaulting to fixup mode.\n");
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+ }
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+
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+ return new_usermode;
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+}
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+
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+#ifdef CONFIG_PROC_FS
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+static const char *usermode_action[] = {
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+ "ignored",
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+ "warn",
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+ "fixup",
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+ "fixup+warn",
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+ "signal",
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+ "signal+warn"
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+};
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+
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+static int alignment_proc_show(struct seq_file *m, void *v)
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+{
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+ seq_printf(m, "User:\t\t%lu\n", ai_user);
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+ seq_printf(m, "System:\t\t%lu\n", ai_sys);
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韩正义