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@@ -0,0 +1,87 @@
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+/*
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+ * Copyright © 2006, Intel Corporation.
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms and conditions of the GNU General Public License,
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+ * version 2, as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope it will be useful, but WITHOUT
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+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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+ * more details.
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+ *
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+ * You should have received a copy of the GNU General Public License along with
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+ * this program; if not, write to the Free Software Foundation, Inc.,
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+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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+ *
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+ */
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+#ifndef _ADMA_H
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+#define _ADMA_H
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+#include <linux/types.h>
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+#include <linux/io.h>
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+#include <mach/hardware.h>
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+#include <asm/hardware/iop_adma.h>
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+
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+/* Memory copy units */
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+#define DMA_CCR(chan) (chan->mmr_base + 0x0)
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+#define DMA_CSR(chan) (chan->mmr_base + 0x4)
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+#define DMA_DAR(chan) (chan->mmr_base + 0xc)
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+#define DMA_NDAR(chan) (chan->mmr_base + 0x10)
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+#define DMA_PADR(chan) (chan->mmr_base + 0x14)
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+#define DMA_PUADR(chan) (chan->mmr_base + 0x18)
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+#define DMA_LADR(chan) (chan->mmr_base + 0x1c)
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+#define DMA_BCR(chan) (chan->mmr_base + 0x20)
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+#define DMA_DCR(chan) (chan->mmr_base + 0x24)
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+
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+/* Application accelerator unit */
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+#define AAU_ACR(chan) (chan->mmr_base + 0x0)
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+#define AAU_ASR(chan) (chan->mmr_base + 0x4)
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+#define AAU_ADAR(chan) (chan->mmr_base + 0x8)
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+#define AAU_ANDAR(chan) (chan->mmr_base + 0xc)
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+#define AAU_SAR(src, chan) (chan->mmr_base + (0x10 + ((src) << 2)))
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+#define AAU_DAR(chan) (chan->mmr_base + 0x20)
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+#define AAU_ABCR(chan) (chan->mmr_base + 0x24)
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+#define AAU_ADCR(chan) (chan->mmr_base + 0x28)
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+#define AAU_SAR_EDCR(src_edc) (chan->mmr_base + (0x02c + ((src_edc-4) << 2)))
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+#define AAU_EDCR0_IDX 8
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+#define AAU_EDCR1_IDX 17
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+#define AAU_EDCR2_IDX 26
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+
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+#define DMA0_ID 0
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+#define DMA1_ID 1
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+#define AAU_ID 2
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+
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+struct iop3xx_aau_desc_ctrl {
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+ unsigned int int_en:1;
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+ unsigned int blk1_cmd_ctrl:3;
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+ unsigned int blk2_cmd_ctrl:3;
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+ unsigned int blk3_cmd_ctrl:3;
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+ unsigned int blk4_cmd_ctrl:3;
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+ unsigned int blk5_cmd_ctrl:3;
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+ unsigned int blk6_cmd_ctrl:3;
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+ unsigned int blk7_cmd_ctrl:3;
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+ unsigned int blk8_cmd_ctrl:3;
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+ unsigned int blk_ctrl:2;
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+ unsigned int dual_xor_en:1;
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+ unsigned int tx_complete:1;
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+ unsigned int zero_result_err:1;
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+ unsigned int zero_result_en:1;
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+ unsigned int dest_write_en:1;
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+};
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+
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+struct iop3xx_aau_e_desc_ctrl {
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+ unsigned int reserved:1;
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+ unsigned int blk1_cmd_ctrl:3;
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+ unsigned int blk2_cmd_ctrl:3;
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+ unsigned int blk3_cmd_ctrl:3;
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+ unsigned int blk4_cmd_ctrl:3;
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+ unsigned int blk5_cmd_ctrl:3;
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+ unsigned int blk6_cmd_ctrl:3;
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+ unsigned int blk7_cmd_ctrl:3;
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+ unsigned int blk8_cmd_ctrl:3;
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+ unsigned int reserved2:7;
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+};
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+
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+struct iop3xx_dma_desc_ctrl {
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+ unsigned int pci_transaction:4;
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+ unsigned int int_en:1;
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