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@@ -899,3 +899,145 @@
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/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
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#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
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+#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
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+#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
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+#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
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+#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
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+#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
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+#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
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+#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
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+#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
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+#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
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+#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
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+#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
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+#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
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+#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
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+#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
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+#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
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+#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
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+#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
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+#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
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+#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
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+#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
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+#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
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+#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
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+#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
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+
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+/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF51x processor) */
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+
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+/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
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+#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
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+#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
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+#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
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+#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
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+#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
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+#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
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+#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX)
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+#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val)
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+
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+
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+/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
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+#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
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+#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
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+#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
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+#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
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+#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
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+#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
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+#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
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+#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
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+#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
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+#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
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+#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
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+#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
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+#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
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+#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
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+
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+#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
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+#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
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+#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
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+#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
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+#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
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+#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
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+#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
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+#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
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+#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
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+#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
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+#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
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+#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
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+#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
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+#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
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+
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+/* ==== end from cdefBF534.h ==== */
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+
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+/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
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+
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+#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
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+#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
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+#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
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+#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
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+#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
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+#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
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+
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+#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
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+#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
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+#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
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+#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
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+#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
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+#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
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+#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW)
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+#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val)
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+#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW)
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+#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
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+#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
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+#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
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+#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS)
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+#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
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+#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS)
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+#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
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+#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS)
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+#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
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+#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE)
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+#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
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+#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW)
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+#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
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+#define bfin_read_MISCPORT_HYSTERESIS() bfin_read16(MISCPORT_HYSTERESIS)
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+#define bfin_write_MISCPORT_HYSTERESIS(val) bfin_write16(MISCPORT_HYSTERESIS, val)
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+
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+/* HOST Port Registers */
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+
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+#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
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+#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
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+#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
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+#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
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+#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
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+#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
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+
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+/* Counter Registers */
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+
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+#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
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+#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
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+#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
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+#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
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+#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
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+#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
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+#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
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+#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
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+#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
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+#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
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+#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
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+#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
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+#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
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+#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
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+#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
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+#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
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+
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+/* Security Registers */
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+
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+#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
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+#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
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+#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
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+#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
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+#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
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+#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
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+
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+#endif /* _CDEF_BF512_H */
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韩正义