| 
					
				 | 
			
			
				@@ -167,3 +167,60 @@ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				 #define	IXP4XX_ICLR2_OFFSET	0x28 /* Interrupt IRQ/FIQ Select 2 */ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				 #define IXP4XX_ICIP2_OFFSET     0x2C /* IRQ Status */ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				 #define IXP4XX_ICFP2_OFFSET	0x30 /* FIQ Status */ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_ICEEN_OFFSET	0x34 /* Error High Pri Enable */ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+/* 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ * Interrupt Controller Register Definitions. 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ */ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_INTC_REG(x) ((volatile u32 *)(IXP4XX_INTC_BASE_VIRT+(x))) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_ICPR	IXP4XX_INTC_REG(IXP4XX_ICPR_OFFSET) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_ICMR     IXP4XX_INTC_REG(IXP4XX_ICMR_OFFSET) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_ICLR     IXP4XX_INTC_REG(IXP4XX_ICLR_OFFSET) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_ICIP     IXP4XX_INTC_REG(IXP4XX_ICIP_OFFSET) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_ICFP     IXP4XX_INTC_REG(IXP4XX_ICFP_OFFSET) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_ICHR     IXP4XX_INTC_REG(IXP4XX_ICHR_OFFSET) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_ICIH     IXP4XX_INTC_REG(IXP4XX_ICIH_OFFSET)  
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_ICFH     IXP4XX_INTC_REG(IXP4XX_ICFH_OFFSET) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_ICPR2	IXP4XX_INTC_REG(IXP4XX_ICPR2_OFFSET) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_ICMR2    IXP4XX_INTC_REG(IXP4XX_ICMR2_OFFSET) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_ICLR2    IXP4XX_INTC_REG(IXP4XX_ICLR2_OFFSET) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_ICIP2    IXP4XX_INTC_REG(IXP4XX_ICIP2_OFFSET) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_ICFP2    IXP4XX_INTC_REG(IXP4XX_ICFP2_OFFSET) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_ICEEN    IXP4XX_INTC_REG(IXP4XX_ICEEN_OFFSET) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+                                                                                 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+/* 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ * Constants to make it easy to access GPIO registers 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ */ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_GPIO_GPOUTR_OFFSET       0x00 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_GPIO_GPOER_OFFSET        0x04 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_GPIO_GPINR_OFFSET        0x08 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_GPIO_GPISR_OFFSET        0x0C 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_GPIO_GPIT1R_OFFSET	0x10 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_GPIO_GPIT2R_OFFSET	0x14 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_GPIO_GPCLKR_OFFSET	0x18 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_GPIO_GPDBSELR_OFFSET	0x1C 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+/*  
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ * GPIO Register Definitions. 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ * [Only perform 32bit reads/writes] 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ */ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_GPIO_REG(x) ((volatile u32 *)(IXP4XX_GPIO_BASE_VIRT+(x))) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_GPIO_GPOUTR	IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOUTR_OFFSET) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_GPIO_GPOER       IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOER_OFFSET) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_GPIO_GPINR       IXP4XX_GPIO_REG(IXP4XX_GPIO_GPINR_OFFSET) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_GPIO_GPISR       IXP4XX_GPIO_REG(IXP4XX_GPIO_GPISR_OFFSET) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_GPIO_GPIT1R      IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT1R_OFFSET) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_GPIO_GPIT2R      IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT2R_OFFSET) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_GPIO_GPCLKR      IXP4XX_GPIO_REG(IXP4XX_GPIO_GPCLKR_OFFSET) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define IXP4XX_GPIO_GPDBSELR    IXP4XX_GPIO_REG(IXP4XX_GPIO_GPDBSELR_OFFSET) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+/* 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ * GPIO register bit definitions 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ */ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+/* Interrupt styles 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ */ 
			 |