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@@ -1627,3 +1627,96 @@ static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
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{ .irq = -1 }
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};
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+static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
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+ { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
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+ { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
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+ { .dma_req = -1 }
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+};
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+
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+static struct omap_hwmod omap44xx_i2c4_hwmod = {
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+ .name = "i2c4",
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+ .class = &omap44xx_i2c_hwmod_class,
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+ .clkdm_name = "l4_per_clkdm",
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+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
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+ .mpu_irqs = omap44xx_i2c4_irqs,
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+ .sdma_reqs = omap44xx_i2c4_sdma_reqs,
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+ .main_clk = "i2c4_fck",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
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+ .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
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+ .modulemode = MODULEMODE_SWCTRL,
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+ },
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+ },
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+ .dev_attr = &i2c_dev_attr,
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+};
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+
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+/*
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+ * 'ipu' class
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+ * imaging processor unit
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+ */
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+
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+static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
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+ .name = "ipu",
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+};
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+
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+/* ipu */
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+static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
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+ { .irq = 100 + OMAP44XX_IRQ_GIC_START },
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+ { .irq = -1 }
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+};
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+
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+static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
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+ { .name = "cpu0", .rst_shift = 0 },
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+ { .name = "cpu1", .rst_shift = 1 },
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+};
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+
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+static struct omap_hwmod omap44xx_ipu_hwmod = {
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+ .name = "ipu",
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+ .class = &omap44xx_ipu_hwmod_class,
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+ .clkdm_name = "ducati_clkdm",
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+ .mpu_irqs = omap44xx_ipu_irqs,
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+ .rst_lines = omap44xx_ipu_resets,
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+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
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+ .main_clk = "ducati_clk_mux_ck",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
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+ .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
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+ .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
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+ .modulemode = MODULEMODE_HWCTRL,
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+ },
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+ },
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+};
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+
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+/*
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+ * 'iss' class
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+ * external images sensor pixel data processor
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+ */
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+
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+static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
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+ .rev_offs = 0x0000,
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+ .sysc_offs = 0x0010,
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+ /*
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+ * ISS needs 100 OCP clk cycles delay after a softreset before
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+ * accessing sysconfig again.
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+ * The lowest frequency at the moment for L3 bus is 100 MHz, so
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+ * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
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+ *
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+ * TODO: Indicate errata when available.
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+ */
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+ .srst_udelay = 2,
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+ .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
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+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
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+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
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+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
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+ .sysc_fields = &omap_hwmod_sysc_type2,
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+};
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+
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+static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
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+ .name = "iss",
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+ .sysc = &omap44xx_iss_sysc,
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+};
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+
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+/* iss */
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朱涛