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@@ -369,3 +369,89 @@ static const struct clk_ops dss1_fck_ops = {
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.get_parent = &omap2_clksel_find_parent_index,
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.set_parent = &omap2_clksel_set_parent,
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};
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+
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+DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel,
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+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
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+ OMAP24XX_CLKSEL_DSS1_MASK,
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+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
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+ OMAP24XX_EN_DSS1_SHIFT, NULL,
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+ dss1_fck_parent_names, dss1_fck_ops);
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+
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+static const struct clksel_rate dss2_fck_sys_rates[] = {
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+ { .div = 1, .val = 0, .flags = RATE_IN_24XX },
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+ { .div = 0 }
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+};
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+
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+static const struct clksel_rate dss2_fck_48m_rates[] = {
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+ { .div = 1, .val = 1, .flags = RATE_IN_24XX },
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+ { .div = 0 }
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+};
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+
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+static const struct clksel_rate func_48m_apll96_rates[] = {
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+ { .div = 2, .val = 0, .flags = RATE_IN_24XX },
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+ { .div = 0 }
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+};
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+
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+static const struct clksel_rate func_48m_alt_rates[] = {
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+ { .div = 1, .val = 1, .flags = RATE_IN_24XX },
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+ { .div = 0 }
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+};
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+
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+static const struct clksel func_48m_clksel[] = {
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+ { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
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+ { .parent = &alt_ck, .rates = func_48m_alt_rates },
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+ { .parent = NULL },
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+};
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+
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+static const char *func_48m_ck_parent_names[] = {
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+ "apll96_ck", "alt_ck",
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+};
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+
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+static struct clk func_48m_ck;
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+
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+static const struct clk_ops func_48m_ck_ops = {
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+ .init = &omap2_init_clk_clkdm,
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+ .recalc_rate = &omap2_clksel_recalc,
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+ .set_rate = &omap2_clksel_set_rate,
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+ .round_rate = &omap2_clksel_round_rate,
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+ .get_parent = &omap2_clksel_find_parent_index,
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+ .set_parent = &omap2_clksel_set_parent,
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+};
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+
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+static struct clk_hw_omap func_48m_ck_hw = {
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+ .hw = {
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+ .clk = &func_48m_ck,
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+ },
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+ .clksel = func_48m_clksel,
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+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
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+ .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
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+ .clkdm_name = "wkup_clkdm",
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+};
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+
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+DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops);
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+
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+static const struct clksel dss2_fck_clksel[] = {
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+ { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
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+ { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
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+ { .parent = NULL },
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+};
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+
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+static const char *dss2_fck_parent_names[] = {
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+ "sys_ck", "func_48m_ck",
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+};
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+
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+DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel,
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+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
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+ OMAP24XX_CLKSEL_DSS2_MASK,
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+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
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+ OMAP24XX_EN_DSS2_SHIFT, NULL,
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+ dss2_fck_parent_names, dss1_fck_ops);
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+
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+static const char *func_54m_ck_parent_names[] = {
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+ "apll54_ck", "alt_ck",
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+};
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+
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+DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0,
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+ OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
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+ OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH,
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+ 0x0, NULL);
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