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@@ -1434,3 +1434,134 @@
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/* DMA Channel 32 Registers */
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#define bfin_read_DMA32_NEXT_DESC_PTR() bfin_read32(DMA32_NEXT_DESC_PTR)
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+#define bfin_write_DMA32_NEXT_DESC_PTR(val) bfin_write32(DMA32_NEXT_DESC_PTR, val)
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+#define bfin_read_DMA32_START_ADDR() bfin_read32(DMA32_START_ADDR)
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+#define bfin_write_DMA32_START_ADDR(val) bfin_write32(DMA32_START_ADDR, val)
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+#define bfin_read_DMA32_CONFIG() bfin_read32(DMA32_CONFIG)
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+#define bfin_write_DMA32_CONFIG(val) bfin_write32(DMA32_CONFIG, val)
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+#define bfin_read_DMA32_X_COUNT() bfin_read32(DMA32_X_COUNT)
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+#define bfin_write_DMA32_X_COUNT(val) bfin_write32(DMA32_X_COUNT, val)
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+#define bfin_read_DMA32_X_MODIFY() bfin_read32(DMA32_X_MODIFY)
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+#define bfin_write_DMA32_X_MODIFY(val) bfin_write32(DMA32_X_MODIFY, val)
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+#define bfin_read_DMA32_Y_COUNT() bfin_read32(DMA32_Y_COUNT)
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+#define bfin_write_DMA32_Y_COUNT(val) bfin_write32(DMA32_Y_COUNT, val)
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+#define bfin_read_DMA32_Y_MODIFY() bfin_read32(DMA32_Y_MODIFY)
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+#define bfin_write_DMA32_Y_MODIFY(val) bfin_write32(DMA32_Y_MODIFY, val)
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+#define bfin_read_DMA32_CURR_DESC_PTR() bfin_read32(DMA32_CURR_DESC_PTR)
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+#define bfin_write_DMA32_CURR_DESC_PTR(val) bfin_write32(DMA32_CURR_DESC_PTR, val)
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+#define bfin_read_DMA32_PREV_DESC_PTR() bfin_read32(DMA32_PREV_DESC_PTR)
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+#define bfin_write_DMA32_PREV_DESC_PTR(val) bfin_write32(DMA32_PREV_DESC_PTR, val)
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+#define bfin_read_DMA32_CURR_ADDR() bfin_read32(DMA32_CURR_ADDR)
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+#define bfin_write_DMA32_CURR_ADDR(val) bfin_write32(DMA32_CURR_ADDR, val)
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+#define bfin_read_DMA32_IRQ_STATUS() bfin_read32(DMA32_IRQ_STATUS)
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+#define bfin_write_DMA32_IRQ_STATUS(val) bfin_write32(DMA32_IRQ_STATUS, val)
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+#define bfin_read_DMA32_CURR_X_COUNT() bfin_read32(DMA32_CURR_X_COUNT)
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+#define bfin_write_DMA32_CURR_X_COUNT(val) bfin_write32(DMA32_CURR_X_COUNT, val)
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+#define bfin_read_DMA32_CURR_Y_COUNT() bfin_read32(DMA32_CURR_Y_COUNT)
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+#define bfin_write_DMA32_CURR_Y_COUNT(val) bfin_write32(DMA32_CURR_Y_COUNT, val)
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+#define bfin_read_DMA32_BWL_COUNT() bfin_read32(DMA32_BWL_COUNT)
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+#define bfin_write_DMA32_BWL_COUNT(val) bfin_write32(DMA32_BWL_COUNT, val)
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+#define bfin_read_DMA32_CURR_BWL_COUNT() bfin_read32(DMA32_CURR_BWL_COUNT)
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+#define bfin_write_DMA32_CURR_BWL_COUNT(val) bfin_write32(DMA32_CURR_BWL_COUNT, val)
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+#define bfin_read_DMA32_BWM_COUNT() bfin_read32(DMA32_BWM_COUNT)
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+#define bfin_write_DMA32_BWM_COUNT(val) bfin_write32(DMA32_BWM_COUNT, val)
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+#define bfin_read_DMA32_CURR_BWM_COUNT() bfin_read32(DMA32_CURR_BWM_COUNT)
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+#define bfin_write_DMA32_CURR_BWM_COUNT(val) bfin_write32(DMA32_CURR_BWM_COUNT, val)
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+
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+/* DMA Channel 33 Registers */
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+
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+#define bfin_read_DMA33_NEXT_DESC_PTR() bfin_read32(DMA33_NEXT_DESC_PTR)
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+#define bfin_write_DMA33_NEXT_DESC_PTR(val) bfin_write32(DMA33_NEXT_DESC_PTR, val)
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+#define bfin_read_DMA33_START_ADDR() bfin_read32(DMA33_START_ADDR)
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+#define bfin_write_DMA33_START_ADDR(val) bfin_write32(DMA33_START_ADDR, val)
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+#define bfin_read_DMA33_CONFIG() bfin_read32(DMA33_CONFIG)
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+#define bfin_write_DMA33_CONFIG(val) bfin_write32(DMA33_CONFIG, val)
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+#define bfin_read_DMA33_X_COUNT() bfin_read32(DMA33_X_COUNT)
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+#define bfin_write_DMA33_X_COUNT(val) bfin_write32(DMA33_X_COUNT, val)
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+#define bfin_read_DMA33_X_MODIFY() bfin_read32(DMA33_X_MODIFY)
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+#define bfin_write_DMA33_X_MODIFY(val) bfin_write32(DMA33_X_MODIFY, val)
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+#define bfin_read_DMA33_Y_COUNT() bfin_read32(DMA33_Y_COUNT)
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+#define bfin_write_DMA33_Y_COUNT(val) bfin_write32(DMA33_Y_COUNT, val)
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+#define bfin_read_DMA33_Y_MODIFY() bfin_read32(DMA33_Y_MODIFY)
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+#define bfin_write_DMA33_Y_MODIFY(val) bfin_write32(DMA33_Y_MODIFY, val)
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+#define bfin_read_DMA33_CURR_DESC_PTR() bfin_read32(DMA33_CURR_DESC_PTR)
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+#define bfin_write_DMA33_CURR_DESC_PTR(val) bfin_write32(DMA33_CURR_DESC_PTR, val)
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+#define bfin_read_DMA33_PREV_DESC_PTR() bfin_read32(DMA33_PREV_DESC_PTR)
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+#define bfin_write_DMA33_PREV_DESC_PTR(val) bfin_write32(DMA33_PREV_DESC_PTR, val)
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+#define bfin_read_DMA33_CURR_ADDR() bfin_read32(DMA33_CURR_ADDR)
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+#define bfin_write_DMA33_CURR_ADDR(val) bfin_write32(DMA33_CURR_ADDR, val)
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+#define bfin_read_DMA33_IRQ_STATUS() bfin_read32(DMA33_IRQ_STATUS)
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+#define bfin_write_DMA33_IRQ_STATUS(val) bfin_write32(DMA33_IRQ_STATUS, val)
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+#define bfin_read_DMA33_CURR_X_COUNT() bfin_read32(DMA33_CURR_X_COUNT)
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+#define bfin_write_DMA33_CURR_X_COUNT(val) bfin_write32(DMA33_CURR_X_COUNT, val)
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+#define bfin_read_DMA33_CURR_Y_COUNT() bfin_read32(DMA33_CURR_Y_COUNT)
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+#define bfin_write_DMA33_CURR_Y_COUNT(val) bfin_write32(DMA33_CURR_Y_COUNT, val)
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+#define bfin_read_DMA33_BWL_COUNT() bfin_read32(DMA33_BWL_COUNT)
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+#define bfin_write_DMA33_BWL_COUNT(val) bfin_write32(DMA33_BWL_COUNT, val)
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+#define bfin_read_DMA33_CURR_BWL_COUNT() bfin_read32(DMA33_CURR_BWL_COUNT)
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+#define bfin_write_DMA33_CURR_BWL_COUNT(val) bfin_write32(DMA33_CURR_BWL_COUNT, val)
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+#define bfin_read_DMA33_BWM_COUNT() bfin_read32(DMA33_BWM_COUNT)
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+#define bfin_write_DMA33_BWM_COUNT(val) bfin_write32(DMA33_BWM_COUNT, val)
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+#define bfin_read_DMA33_CURR_BWM_COUNT() bfin_read32(DMA33_CURR_BWM_COUNT)
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+#define bfin_write_DMA33_CURR_BWM_COUNT(val) bfin_write32(DMA33_CURR_BWM_COUNT, val)
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+
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+/* DMA Channel 34 Registers */
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+
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+#define bfin_read_DMA34_NEXT_DESC_PTR() bfin_read32(DMA34_NEXT_DESC_PTR)
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+#define bfin_write_DMA34_NEXT_DESC_PTR(val) bfin_write32(DMA34_NEXT_DESC_PTR, val)
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+#define bfin_read_DMA34_START_ADDR() bfin_read32(DMA34_START_ADDR)
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+#define bfin_write_DMA34_START_ADDR(val) bfin_write32(DMA34_START_ADDR, val)
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+#define bfin_read_DMA34_CONFIG() bfin_read32(DMA34_CONFIG)
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+#define bfin_write_DMA34_CONFIG(val) bfin_write32(DMA34_CONFIG, val)
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+#define bfin_read_DMA34_X_COUNT() bfin_read32(DMA34_X_COUNT)
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+#define bfin_write_DMA34_X_COUNT(val) bfin_write32(DMA34_X_COUNT, val)
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+#define bfin_read_DMA34_X_MODIFY() bfin_read32(DMA34_X_MODIFY)
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+#define bfin_write_DMA34_X_MODIFY(val) bfin_write32(DMA34_X_MODIFY, val)
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+#define bfin_read_DMA34_Y_COUNT() bfin_read32(DMA34_Y_COUNT)
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+#define bfin_write_DMA34_Y_COUNT(val) bfin_write32(DMA34_Y_COUNT, val)
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+#define bfin_read_DMA34_Y_MODIFY() bfin_read32(DMA34_Y_MODIFY)
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+#define bfin_write_DMA34_Y_MODIFY(val) bfin_write32(DMA34_Y_MODIFY, val)
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+#define bfin_read_DMA34_CURR_DESC_PTR() bfin_read32(DMA34_CURR_DESC_PTR)
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+#define bfin_write_DMA34_CURR_DESC_PTR(val) bfin_write32(DMA34_CURR_DESC_PTR, val)
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+#define bfin_read_DMA34_PREV_DESC_PTR() bfin_read32(DMA34_PREV_DESC_PTR)
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+#define bfin_write_DMA34_PREV_DESC_PTR(val) bfin_write32(DMA34_PREV_DESC_PTR, val)
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+#define bfin_read_DMA34_CURR_ADDR() bfin_read32(DMA34_CURR_ADDR)
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+#define bfin_write_DMA34_CURR_ADDR(val) bfin_write32(DMA34_CURR_ADDR, val)
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+#define bfin_read_DMA34_IRQ_STATUS() bfin_read32(DMA34_IRQ_STATUS)
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+#define bfin_write_DMA34_IRQ_STATUS(val) bfin_write32(DMA34_IRQ_STATUS, val)
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+#define bfin_read_DMA34_CURR_X_COUNT() bfin_read32(DMA34_CURR_X_COUNT)
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+#define bfin_write_DMA34_CURR_X_COUNT(val) bfin_write32(DMA34_CURR_X_COUNT, val)
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+#define bfin_read_DMA34_CURR_Y_COUNT() bfin_read32(DMA34_CURR_Y_COUNT)
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+#define bfin_write_DMA34_CURR_Y_COUNT(val) bfin_write32(DMA34_CURR_Y_COUNT, val)
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+#define bfin_read_DMA34_BWL_COUNT() bfin_read32(DMA34_BWL_COUNT)
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+#define bfin_write_DMA34_BWL_COUNT(val) bfin_write32(DMA34_BWL_COUNT, val)
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+#define bfin_read_DMA34_CURR_BWL_COUNT() bfin_read32(DMA34_CURR_BWL_COUNT)
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+#define bfin_write_DMA34_CURR_BWL_COUNT(val) bfin_write32(DMA34_CURR_BWL_COUNT, val)
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+#define bfin_read_DMA34_BWM_COUNT() bfin_read32(DMA34_BWM_COUNT)
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+#define bfin_write_DMA34_BWM_COUNT(val) bfin_write32(DMA34_BWM_COUNT, val)
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+#define bfin_read_DMA34_CURR_BWM_COUNT() bfin_read32(DMA34_CURR_BWM_COUNT)
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+#define bfin_write_DMA34_CURR_BWM_COUNT(val) bfin_write32(DMA34_CURR_BWM_COUNT, val)
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+
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+/* DMA Channel 35 Registers */
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+
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+#define bfin_read_DMA35_NEXT_DESC_PTR() bfin_read32(DMA35_NEXT_DESC_PTR)
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+#define bfin_write_DMA35_NEXT_DESC_PTR(val) bfin_write32(DMA35_NEXT_DESC_PTR, val)
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+#define bfin_read_DMA35_START_ADDR() bfin_read32(DMA35_START_ADDR)
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+#define bfin_write_DMA35_START_ADDR(val) bfin_write32(DMA35_START_ADDR, val)
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+#define bfin_read_DMA35_CONFIG() bfin_read32(DMA35_CONFIG)
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+#define bfin_write_DMA35_CONFIG(val) bfin_write32(DMA35_CONFIG, val)
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+#define bfin_read_DMA35_X_COUNT() bfin_read32(DMA35_X_COUNT)
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+#define bfin_write_DMA35_X_COUNT(val) bfin_write32(DMA35_X_COUNT, val)
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+#define bfin_read_DMA35_X_MODIFY() bfin_read32(DMA35_X_MODIFY)
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+#define bfin_write_DMA35_X_MODIFY(val) bfin_write32(DMA35_X_MODIFY, val)
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+#define bfin_read_DMA35_Y_COUNT() bfin_read32(DMA35_Y_COUNT)
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+#define bfin_write_DMA35_Y_COUNT(val) bfin_write32(DMA35_Y_COUNT, val)
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+#define bfin_read_DMA35_Y_MODIFY() bfin_read32(DMA35_Y_MODIFY)
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+#define bfin_write_DMA35_Y_MODIFY(val) bfin_write32(DMA35_Y_MODIFY, val)
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+#define bfin_read_DMA35_CURR_DESC_PTR() bfin_read32(DMA35_CURR_DESC_PTR)
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+#define bfin_write_DMA35_CURR_DESC_PTR(val) bfin_write32(DMA35_CURR_DESC_PTR, val)
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+#define bfin_read_DMA35_PREV_DESC_PTR() bfin_read32(DMA35_PREV_DESC_PTR)
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+#define bfin_write_DMA35_PREV_DESC_PTR(val) bfin_write32(DMA35_PREV_DESC_PTR, val)
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+#define bfin_read_DMA35_CURR_ADDR() bfin_read32(DMA35_CURR_ADDR)
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+#define bfin_write_DMA35_CURR_ADDR(val) bfin_write32(DMA35_CURR_ADDR, val)
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+#define bfin_read_DMA35_IRQ_STATUS() bfin_read32(DMA35_IRQ_STATUS)
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