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@@ -1486,3 +1486,163 @@
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#define OTP_DATA0 0xffc04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
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#define OTP_DATA1 0xffc04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
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+#define OTP_DATA2 0xffc04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
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+#define OTP_DATA3 0xffc0438c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
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+
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+/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 processor */
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+
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+/* ********************************************************** */
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+/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
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+/* and MULTI BIT READ MACROS */
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+/* ********************************************************** */
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+
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+/* SIC_IMASK Masks */
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+#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
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+#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
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+#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
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+#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
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+
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+/* SIC_IWR Masks */
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+#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
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+#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
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+#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
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+#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
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+
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+/* Bit masks for SIC_IAR0 */
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+
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+#define PLL_WAKEUP 0x1 /* PLL Wakeup */
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+
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+/* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */
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+
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+#define DMA0_ERR 0x2 /* DMA Controller 0 Error */
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+#define EPPI0_ERR 0x4 /* EPPI0 Error */
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+#define SPORT0_ERR 0x8 /* SPORT0 Error */
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+#define SPORT1_ERR 0x10 /* SPORT1 Error */
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+#define SPI0_ERR 0x20 /* SPI0 Error */
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+#define UART0_ERR 0x40 /* UART0 Error */
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+#define RTC 0x80 /* Real-Time Clock */
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+#define DMA12 0x100 /* DMA Channel 12 */
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+#define DMA0 0x200 /* DMA Channel 0 */
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+#define DMA1 0x400 /* DMA Channel 1 */
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+#define DMA2 0x800 /* DMA Channel 2 */
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+#define DMA3 0x1000 /* DMA Channel 3 */
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+#define DMA4 0x2000 /* DMA Channel 4 */
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+#define DMA6 0x4000 /* DMA Channel 6 */
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+#define DMA7 0x8000 /* DMA Channel 7 */
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+#define PINT0 0x80000 /* Pin Interrupt 0 */
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+#define PINT1 0x100000 /* Pin Interrupt 1 */
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+#define MDMA0 0x200000 /* Memory DMA Stream 0 */
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+#define MDMA1 0x400000 /* Memory DMA Stream 1 */
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+#define WDOG 0x800000 /* Watchdog Timer */
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+#define DMA1_ERR 0x1000000 /* DMA Controller 1 Error */
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+#define SPORT2_ERR 0x2000000 /* SPORT2 Error */
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+#define SPORT3_ERR 0x4000000 /* SPORT3 Error */
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+#define MXVR_SD 0x8000000 /* MXVR Synchronous Data */
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+#define SPI1_ERR 0x10000000 /* SPI1 Error */
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+#define SPI2_ERR 0x20000000 /* SPI2 Error */
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+#define UART1_ERR 0x40000000 /* UART1 Error */
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+#define UART2_ERR 0x80000000 /* UART2 Error */
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+
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+/* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */
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+
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+#define CAN0_ERR 0x1 /* CAN0 Error */
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+#define DMA18 0x2 /* DMA Channel 18 */
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+#define DMA19 0x4 /* DMA Channel 19 */
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+#define DMA20 0x8 /* DMA Channel 20 */
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+#define DMA21 0x10 /* DMA Channel 21 */
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+#define DMA13 0x20 /* DMA Channel 13 */
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+#define DMA14 0x40 /* DMA Channel 14 */
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+#define DMA5 0x80 /* DMA Channel 5 */
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+#define DMA23 0x100 /* DMA Channel 23 */
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+#define DMA8 0x200 /* DMA Channel 8 */
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+#define DMA9 0x400 /* DMA Channel 9 */
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+#define DMA10 0x800 /* DMA Channel 10 */
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+#define DMA11 0x1000 /* DMA Channel 11 */
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+#define TWI0 0x2000 /* TWI0 */
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+#define TWI1 0x4000 /* TWI1 */
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+#define CAN0_RX 0x8000 /* CAN0 Receive */
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+#define CAN0_TX 0x10000 /* CAN0 Transmit */
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+#define MDMA2 0x20000 /* Memory DMA Stream 0 */
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+#define MDMA3 0x40000 /* Memory DMA Stream 1 */
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+#define MXVR_STAT 0x80000 /* MXVR Status */
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+#define MXVR_CM 0x100000 /* MXVR Control Message */
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+#define MXVR_AP 0x200000 /* MXVR Asynchronous Packet */
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+#define EPPI1_ERR 0x400000 /* EPPI1 Error */
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+#define EPPI2_ERR 0x800000 /* EPPI2 Error */
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+#define UART3_ERR 0x1000000 /* UART3 Error */
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+#define HOST_ERR 0x2000000 /* Host DMA Port Error */
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+#define USB_ERR 0x4000000 /* USB Error */
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+#define PIXC_ERR 0x8000000 /* Pixel Compositor Error */
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+#define NFC_ERR 0x10000000 /* Nand Flash Controller Error */
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+#define ATAPI_ERR 0x20000000 /* ATAPI Error */
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+#define CAN1_ERR 0x40000000 /* CAN1 Error */
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+#define DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */
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+#define DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */
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+#define DMAR0 0x80000000 /* DMAR0 Block */
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+#define DMAR1 0x80000000 /* DMAR1 Block */
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+
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+/* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */
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+
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+#define DMA15 0x1 /* DMA Channel 15 */
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+#define DMA16 0x2 /* DMA Channel 16 */
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+#define DMA17 0x4 /* DMA Channel 17 */
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+#define DMA22 0x8 /* DMA Channel 22 */
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+#define CNT 0x10 /* Counter */
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+#define KEY 0x20 /* Keypad */
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+#define CAN1_RX 0x40 /* CAN1 Receive */
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+#define CAN1_TX 0x80 /* CAN1 Transmit */
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+#define SDH_INT_MASK0 0x100 /* SDH Mask 0 */
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+#define SDH_INT_MASK1 0x200 /* SDH Mask 1 */
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+#define USB_EINT 0x400 /* USB Exception */
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+#define USB_INT0 0x800 /* USB Interrupt 0 */
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+#define USB_INT1 0x1000 /* USB Interrupt 1 */
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+#define USB_INT2 0x2000 /* USB Interrupt 2 */
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+#define USB_DMAINT 0x4000 /* USB DMA */
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+#define OTPSEC 0x8000 /* OTP Access Complete */
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+#define TIMER0 0x400000 /* Timer 0 */
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+#define TIMER1 0x800000 /* Timer 1 */
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+#define TIMER2 0x1000000 /* Timer 2 */
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+#define TIMER3 0x2000000 /* Timer 3 */
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+#define TIMER4 0x4000000 /* Timer 4 */
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+#define TIMER5 0x8000000 /* Timer 5 */
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+#define TIMER6 0x10000000 /* Timer 6 */
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+#define TIMER7 0x20000000 /* Timer 7 */
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+#define PINT2 0x40000000 /* Pin Interrupt 2 */
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+#define PINT3 0x80000000 /* Pin Interrupt 3 */
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+
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+/* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
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+
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+#define CTYPE 0x40 /* DMA Channel Type */
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+#define PMAP 0xf000 /* Peripheral Mapped To This Channel */
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+
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+/* Bit masks for DMACx_TC_PER */
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+
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+#define DCB_TRAFFIC_PERIOD 0xf /* DCB Traffic Control Period */
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+#define DEB_TRAFFIC_PERIOD 0xf0 /* DEB Traffic Control Period */
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+#define DAB_TRAFFIC_PERIOD 0x700 /* DAB Traffic Control Period */
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+#define MDMA_ROUND_ROBIN_PERIOD 0xf800 /* MDMA Round Robin Period */
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+
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+/* Bit masks for DMACx_TC_CNT */
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+
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+#define DCB_TRAFFIC_COUNT 0xf /* DCB Traffic Control Count */
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+#define DEB_TRAFFIC_COUNT 0xf0 /* DEB Traffic Control Count */
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+#define DAB_TRAFFIC_COUNT 0x700 /* DAB Traffic Control Count */
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+#define MDMA_ROUND_ROBIN_COUNT 0xf800 /* MDMA Round Robin Count */
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+
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+/* Bit masks for DMAC1_PERIMUX */
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+
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+#define PMUXSDH 0x1 /* Peripheral Select for DMA22 channel */
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+
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+/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
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+/* EBIU_AMGCTL Masks */
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+#define AMCKEN 0x0001 /* Enable CLKOUT */
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+#define AMBEN_NONE 0x0000 /* All Banks Disabled */
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+#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
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+#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
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+#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
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+#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
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+
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+
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+/* Bit masks for EBIU_AMBCTL0 */
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+
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+#define B0RDYEN 0x1 /* Bank 0 ARDY Enable */
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吉超博