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@@ -445,3 +445,135 @@
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#define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */
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#define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */
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#define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */
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+#define SDCR0_SCD 0x00000020 /* Sample Clock Direction select */
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+ /* (GPIO [16]) */
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+#define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */
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+#define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */
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+#define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */
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+#define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */
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+#define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */
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+#define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */
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+#define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */
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+#define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */
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+
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+#define SDCR1_AAF 0x00000001 /* Abort After Frame enable */
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+ /* (GPIO [17]) */
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+#define SDCR1_TXE 0x00000002 /* Transmit Enable */
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+#define SDCR1_RXE 0x00000004 /* Receive Enable */
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+#define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
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+ /* more Interrupt Enable */
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+#define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
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+ /* Interrupt Enable */
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+#define SDCR1_AME 0x00000020 /* Address Match Enable */
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+#define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */
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+#define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */
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+#define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */
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+#define SDCR1_RAE 0x00000080 /* Receive Abort interrupt Enable */
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+
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+#define SDCR2_AMV Fld (8, 0) /* Address Match Value */
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+
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+#define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
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+#define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
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+ /* fsd = fxtl/(16*(BRD[11:0] + 1)) */
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+ /* Tsd = 16*(BRD[11:0] + 1)*Txtl */
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+#define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
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+ (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \
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+ FShft (SDCR3_BRD))
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+#define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
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+ (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \
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+ FShft (SDCR4_BRD))
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+ /* fsd = fxtl/(16*Floor (Div/16)) */
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+ /* Tsd = 16*Floor (Div/16)*Txtl */
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+#define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
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+ (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \
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+ FShft (SDCR3_BRD))
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+#define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
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+ (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \
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+ FShft (SDCR4_BRD))
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+ /* fsd = fxtl/(16*Ceil (Div/16)) */
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+ /* Tsd = 16*Ceil (Div/16)*Txtl */
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+
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+#define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
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+#if 0 /* Hidden receive FIFO bits */
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+#define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
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+#define SDDR_CRE 0x00000200 /* receive CRC Error (read) */
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+#define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
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+#endif /* 0 */
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+
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+#define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */
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+#define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
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+#define SDSR0_RAB 0x00000004 /* Receive ABort */
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+#define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
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+ /* Service request (read) */
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+#define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */
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+ /* more Service request (read) */
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+
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+#define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
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+#define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */
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+#define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
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+#define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
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+#define SDSR1_RTD 0x00000010 /* Receive Transition Detected */
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+#define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */
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+#define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */
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+#define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */
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+
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+
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+/*
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+ * High-Speed Serial to Parallel controller (HSSP) control registers
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+ *
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+ * Registers
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+ * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel
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+ * controller (HSSP) Control Register 0 (read/write).
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+ * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel
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+ * controller (HSSP) Control Register 1 (read/write).
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+ * Ser2HSDR Serial port 2 High-Speed Serial to Parallel
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+ * controller (HSSP) Data Register (read/write).
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+ * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel
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+ * controller (HSSP) Status Register 0 (read/write).
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+ * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel
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+ * controller (HSSP) Status Register 1 (read).
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+ * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel
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+ * controller (HSSP) Control Register 2 (read/write).
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+ * [The HSCR2 register is only implemented in
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+ * versions 2.0 (rev. = 8) and higher of the StrongARM
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+ * SA-1100.]
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+ */
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+
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+#define Ser2HSCR0 __REG(0x80040060) /* Ser. port 2 HSSP Control Reg. 0 */
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+#define Ser2HSCR1 __REG(0x80040064) /* Ser. port 2 HSSP Control Reg. 1 */
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+#define Ser2HSDR __REG(0x8004006C) /* Ser. port 2 HSSP Data Reg. */
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+#define Ser2HSSR0 __REG(0x80040074) /* Ser. port 2 HSSP Status Reg. 0 */
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+#define Ser2HSSR1 __REG(0x80040078) /* Ser. port 2 HSSP Status Reg. 1 */
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+#define Ser2HSCR2 __REG(0x90060028) /* Ser. port 2 HSSP Control Reg. 2 */
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+
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+#define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */
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+#define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */
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+#define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */
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+#define HSCR0_LBM 0x00000002 /* Look-Back Mode */
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+#define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */
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+#define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */
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+#define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */
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+#define HSCR0_TXE 0x00000008 /* Transmit Enable */
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+#define HSCR0_RXE 0x00000010 /* Receive Enable */
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+#define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */
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+ /* more Interrupt Enable */
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+#define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */
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+ /* Interrupt Enable */
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+#define HSCR0_AME 0x00000080 /* Address Match Enable */
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+
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+#define HSCR1_AMV Fld (8, 0) /* Address Match Value */
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+
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+#define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
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+#if 0 /* Hidden receive FIFO bits */
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+#define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
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+#define HSDR_CRE 0x00000200 /* receive CRC Error (read) */
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+#define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
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+#endif /* 0 */
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+
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+#define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */
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+#define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
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+#define HSSR0_RAB 0x00000004 /* Receive ABort */
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+#define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
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+ /* Service request (read) */
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+#define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */
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+ /* more Service request (read) */
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沈瑞清