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@@ -330,3 +330,29 @@ struct bfin_uart_regs {
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#define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR)
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#define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR)
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#define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL)
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#define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL)
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#define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH)
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#define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH)
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+#define UART_GET_CLK(p) ((UART_GET_DLH(p) << 8) | UART_GET_DLL(p))
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+#define UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL)
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+#define UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR)
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+#define UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR)
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+#define UART_GET_MSR(p) bfin_read16(port_membase(p) + OFFSET_MSR)
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+
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+#define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v)
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+#define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v)
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+#define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v)
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+#define UART_PUT_CLK(p, v) do \
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+{\
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+UART_PUT_DLL(p, v & 0xFF); \
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+UART_PUT_DLH(p, (v >> 8) & 0xFF); } while (0);
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+
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+#define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v)
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+#define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v)
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+#define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v)
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+
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+#ifdef BFIN_UART_BF54X_STYLE
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+
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+#define UART_CLEAR_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_CLEAR, v)
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+#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER_SET)
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+#define UART_SET_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_SET, v)
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+
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+#define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF54x */
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+#define UART_SET_DLAB(p) /* MMRs not muxed on BF54x */
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