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@@ -219,3 +219,139 @@ struct thread_struct {
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/* Saved state of the DSP ASE, if available. */
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/* Saved state of the DSP ASE, if available. */
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struct mips_dsp_state dsp;
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struct mips_dsp_state dsp;
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+ /* Saved watch register state, if available. */
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+ union mips_watch_reg_state watch;
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+
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+ /* Other stuff associated with the thread. */
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+ unsigned long cp0_badvaddr; /* Last user fault */
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+ unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
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+ unsigned long error_code;
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+#ifdef CONFIG_CPU_CAVIUM_OCTEON
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+ struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
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+ struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
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+#endif
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+ struct mips_abi *abi;
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+};
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+
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+#ifdef CONFIG_MIPS_MT_FPAFF
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+#define FPAFF_INIT \
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+ .emulated_fp = 0, \
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+ .user_cpus_allowed = INIT_CPUMASK,
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+#else
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+#define FPAFF_INIT
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+#endif /* CONFIG_MIPS_MT_FPAFF */
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+
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+#ifdef CONFIG_CPU_CAVIUM_OCTEON
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+#define OCTEON_INIT \
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+ .cp2 = INIT_OCTEON_COP2,
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+#else
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+#define OCTEON_INIT
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+#endif /* CONFIG_CPU_CAVIUM_OCTEON */
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+
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+#define INIT_THREAD { \
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+ /* \
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+ * Saved main processor registers \
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+ */ \
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+ .reg16 = 0, \
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+ .reg17 = 0, \
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+ .reg18 = 0, \
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+ .reg19 = 0, \
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+ .reg20 = 0, \
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+ .reg21 = 0, \
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+ .reg22 = 0, \
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+ .reg23 = 0, \
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+ .reg29 = 0, \
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+ .reg30 = 0, \
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+ .reg31 = 0, \
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+ /* \
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+ * Saved cp0 stuff \
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+ */ \
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+ .cp0_status = 0, \
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+ /* \
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+ * Saved FPU/FPU emulator stuff \
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+ */ \
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+ .fpu = { \
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+ .fpr = {0,}, \
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+ .fcr31 = 0, \
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+ }, \
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+ /* \
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+ * FPU affinity state (null if not FPAFF) \
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+ */ \
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+ FPAFF_INIT \
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+ /* \
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+ * Saved DSP stuff \
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+ */ \
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+ .dsp = { \
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+ .dspr = {0, }, \
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+ .dspcontrol = 0, \
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+ }, \
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+ /* \
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+ * saved watch register stuff \
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+ */ \
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+ .watch = {{{0,},},}, \
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+ /* \
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+ * Other stuff associated with the process \
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+ */ \
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+ .cp0_badvaddr = 0, \
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+ .cp0_baduaddr = 0, \
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+ .error_code = 0, \
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+ /* \
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+ * Cavium Octeon specifics (null if not Octeon) \
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+ */ \
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+ OCTEON_INIT \
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+}
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+
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+struct task_struct;
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+
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+/* Free all resources held by a thread. */
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+#define release_thread(thread) do { } while(0)
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+
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+extern unsigned long thread_saved_pc(struct task_struct *tsk);
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+
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+/*
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+ * Do necessary setup to start up a newly executed thread.
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+ */
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+extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
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+
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+unsigned long get_wchan(struct task_struct *p);
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+
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+#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
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+ THREAD_SIZE - 32 - sizeof(struct pt_regs))
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+#define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
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+#define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
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+#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
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+#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
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+
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+#define cpu_relax() barrier()
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+
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+/*
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+ * Return_address is a replacement for __builtin_return_address(count)
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+ * which on certain architectures cannot reasonably be implemented in GCC
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+ * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386).
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+ * Note that __builtin_return_address(x>=1) is forbidden because GCC
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+ * aborts compilation on some CPUs. It's simply not possible to unwind
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+ * some CPU's stackframes.
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+ *
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+ * __builtin_return_address works only for non-leaf functions. We avoid the
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+ * overhead of a function call by forcing the compiler to save the return
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+ * address register on the stack.
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+ */
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+#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
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+
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+#ifdef CONFIG_CPU_HAS_PREFETCH
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+
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+#define ARCH_HAS_PREFETCH
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+#define prefetch(x) __builtin_prefetch((x), 0, 1)
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+
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+#define ARCH_HAS_PREFETCHW
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+#define prefetchw(x) __builtin_prefetch((x), 1, 1)
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+
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+/*
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+ * See Documentation/scheduler/sched-arch.txt; prevents deadlock on SMP
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+ * systems.
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+ */
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+#define __ARCH_WANT_UNLOCKED_CTXSW
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+
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+#endif
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+
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+#endif /* _ASM_PROCESSOR_H */
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