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@@ -0,0 +1,80 @@
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+#ifndef _OPSPUT_OPSPUT_PLD_H
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+#define _OPSPUT_OPSPUT_PLD_H
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+
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+/*
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+ * include/asm-m32r/opsput/opsput_pld.h
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+ *
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+ * Definitions for Programmable Logic Device(PLD) on OPSPUT board.
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+ *
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+ * Copyright (c) 2002 Takeo Takahashi
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+ *
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+ * This file is subject to the terms and conditions of the GNU General
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+ * Public License. See the file "COPYING" in the main directory of
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+ * this archive for more details.
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+ */
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+
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+#define PLD_PLAT_BASE 0x1cc00000
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+
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+#ifndef __ASSEMBLY__
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+/*
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+ * C functions use non-cache address.
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+ */
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+#define PLD_BASE (PLD_PLAT_BASE /* + NONCACHE_OFFSET */)
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+#define __reg8 (volatile unsigned char *)
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+#define __reg16 (volatile unsigned short *)
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+#define __reg32 (volatile unsigned int *)
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+#else
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+#define PLD_BASE (PLD_PLAT_BASE + NONCACHE_OFFSET)
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+#define __reg8
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+#define __reg16
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+#define __reg32
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+#endif /* __ASSEMBLY__ */
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+
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+/* CFC */
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+#define PLD_CFRSTCR __reg16(PLD_BASE + 0x0000)
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+#define PLD_CFSTS __reg16(PLD_BASE + 0x0002)
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+#define PLD_CFIMASK __reg16(PLD_BASE + 0x0004)
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+#define PLD_CFBUFCR __reg16(PLD_BASE + 0x0006)
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+#define PLD_CFVENCR __reg16(PLD_BASE + 0x0008)
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+#define PLD_CFCR0 __reg16(PLD_BASE + 0x000a)
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+#define PLD_CFCR1 __reg16(PLD_BASE + 0x000c)
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+#define PLD_IDERSTCR __reg16(PLD_BASE + 0x0010)
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+
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+/* MMC */
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+#define PLD_MMCCR __reg16(PLD_BASE + 0x4000)
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+#define PLD_MMCMOD __reg16(PLD_BASE + 0x4002)
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+#define PLD_MMCSTS __reg16(PLD_BASE + 0x4006)
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+#define PLD_MMCBAUR __reg16(PLD_BASE + 0x400a)
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+#define PLD_MMCCMDBCUT __reg16(PLD_BASE + 0x400c)
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+#define PLD_MMCCDTBCUT __reg16(PLD_BASE + 0x400e)
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+#define PLD_MMCDET __reg16(PLD_BASE + 0x4010)
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+#define PLD_MMCWP __reg16(PLD_BASE + 0x4012)
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+#define PLD_MMCWDATA __reg16(PLD_BASE + 0x5000)
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+#define PLD_MMCRDATA __reg16(PLD_BASE + 0x6000)
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+#define PLD_MMCCMDDATA __reg16(PLD_BASE + 0x7000)
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+#define PLD_MMCRSPDATA __reg16(PLD_BASE + 0x7006)
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+
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+/* ICU
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+ * ICUISTS: status register
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+ * ICUIREQ0: request register
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+ * ICUIREQ1: request register
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+ * ICUCR3: control register for CFIREQ# interrupt
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+ * ICUCR4: control register for CFC Card insert interrupt
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+ * ICUCR5: control register for CFC Card eject interrupt
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+ * ICUCR6: control register for external interrupt
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+ * ICUCR11: control register for MMC Card insert/eject interrupt
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+ * ICUCR13: control register for SC error interrupt
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+ * ICUCR14: control register for SC receive interrupt
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+ * ICUCR15: control register for SC send interrupt
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+ * ICUCR16: control register for SIO0 receive interrupt
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+ * ICUCR17: control register for SIO0 send interrupt
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+ */
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+#if !defined(CONFIG_PLAT_USRV)
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+#define PLD_IRQ_INT0 (OPSPUT_PLD_IRQ_BASE + 0) /* None */
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+#define PLD_IRQ_INT1 (OPSPUT_PLD_IRQ_BASE + 1) /* reserved */
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+#define PLD_IRQ_INT2 (OPSPUT_PLD_IRQ_BASE + 2) /* reserved */
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+#define PLD_IRQ_CFIREQ (OPSPUT_PLD_IRQ_BASE + 3) /* CF IREQ */
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+#define PLD_IRQ_CFC_INSERT (OPSPUT_PLD_IRQ_BASE + 4) /* CF Insert */
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+#define PLD_IRQ_CFC_EJECT (OPSPUT_PLD_IRQ_BASE + 5) /* CF Eject */
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+#define PLD_IRQ_EXINT (OPSPUT_PLD_IRQ_BASE + 6) /* EXINT */
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+#define PLD_IRQ_INT7 (OPSPUT_PLD_IRQ_BASE + 7) /* reserved */
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朱涛