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@@ -453,3 +453,72 @@ static struct intc_vect intcs_vectors[] = {
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/* MFI */
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/* BBIF2 */
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INTCS_VECT(VPU5F, 0x0980),
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+ INTCS_VECT(_2DG_BRK_INT, 0x09A0),
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+ /* SGX540 */
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+ /* 2DDMAC */
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+ /* IPMMU */
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+ /* RTDMAC(2) */
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+ /* KEYSC */
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+ /* MSIOF */
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+ INTCS_VECT(IIC0_ALI, 0x0E00),
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+ INTCS_VECT(IIC0_TACKI, 0x0E20),
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+ INTCS_VECT(IIC0_WAITI, 0x0E40),
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+ INTCS_VECT(IIC0_DTEI, 0x0E60),
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+ INTCS_VECT(TMU0_0, 0x0E80),
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+ INTCS_VECT(TMU0_1, 0x0EA0),
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+ INTCS_VECT(TMU0_2, 0x0EC0),
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+ INTCS_VECT(CMT0, 0x0F00),
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+ /* CMT2 */
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+ INTCS_VECT(LMB, 0x0F60),
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+ INTCS_VECT(CTI, 0x0400),
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+ INTCS_VECT(VOU, 0x0420),
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+ /* RWDT0 */
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+ INTCS_VECT(ICB, 0x0480),
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+ INTCS_VECT(VIO6C, 0x04E0),
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+ INTCS_VECT(CEU20, 0x0500),
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+ INTCS_VECT(CEU21, 0x0520),
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+ INTCS_VECT(JPU, 0x0560),
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+ INTCS_VECT(LCDC0, 0x0580),
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+ INTCS_VECT(LCRC, 0x05A0),
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+ /* RTDMAC2(1) */
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+ /* RTDMAC2(2) */
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+ INTCS_VECT(LCDC1, 0x1780),
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+ /* SPU2 */
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+ /* FSI */
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+ /* FMSI */
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+ INTCS_VECT(TMU1_0, 0x1900),
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+ INTCS_VECT(TMU1_1, 0x1920),
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+ INTCS_VECT(TMU1_2, 0x1940),
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+ INTCS_VECT(CMT4, 0x1980),
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+ INTCS_VECT(DISP, 0x19A0),
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+ INTCS_VECT(DSRV, 0x19C0),
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+ /* MFIS2 */
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+ INTCS_VECT(CPORTS2R, 0x1A20),
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+
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+ INTC_VECT(INTCS, 0xf80),
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+};
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+
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+static struct intc_group intcs_groups[] __initdata = {
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+ INTC_GROUP(_2DG1, /*FIXME*/
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+ _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP),
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+ INTC_GROUP(IIC0,
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+ IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI),
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+ INTC_GROUP(TMU1,
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+ TMU1_0, TMU1_1, TMU1_2),
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+};
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+
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+static struct intc_mask_reg intcs_mask_registers[] = {
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+ /* IMR0SA / IMCR0SA */ /* all 0 */
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+ { /* IMR1SA / IMCR1SA */ 0xffd20184, 0xffd201c4, 8,
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+ { _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP, VPU5HA2,
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+ 0, 0, 0, 0 /*STPRO*/ } },
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+ { /* IMR2SA / IMCR2SA */ 0xffd20188, 0xffd201c8, 8,
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+ { 0/*STPRO*/, 0, CEU21, VPU5F,
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+ 0/*BBIF2*/, 0, 0, 0/*MFI*/ } },
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+ { /* IMR3SA / IMCR3SA */ 0xffd2018c, 0xffd201cc, 8,
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+ { 0, 0, 0, 0, /*2DDMAC*/
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+ VIO6C, 0, 0, ICB } },
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+ { /* IMR4SA / IMCR4SA */ 0xffd20190, 0xffd201d0, 8,
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+ { 0, 0, VOU, CTI,
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+ JPU, 0, LCRC, LCDC0 } },
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+ /* IMR5SA / IMCR5SA */ /*KEYSC/RTDMAC2/RTDMAC1*/
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