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@@ -75,3 +75,111 @@ static struct map_desc u8500_io_desc[] __initdata = {
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/* U9540 IO map specific description */
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static struct map_desc u9540_io_desc[] __initdata = {
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__IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K + SZ_8K),
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+ __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K + SZ_8K),
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+};
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+
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+void __init u8500_map_io(void)
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+{
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+ /*
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+ * Map the UARTs early so that the DEBUG_LL stuff continues to work.
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+ */
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+ iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc));
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+
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+ ux500_map_io();
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+
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+ iotable_init(u8500_common_io_desc, ARRAY_SIZE(u8500_common_io_desc));
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+
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+ if (cpu_is_ux540_family())
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+ iotable_init(u9540_io_desc, ARRAY_SIZE(u9540_io_desc));
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+ else
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+ iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
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+
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+ _PRCMU_BASE = __io_address(U8500_PRCMU_BASE);
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+}
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+
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+static struct resource db8500_pmu_resources[] = {
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+ [0] = {
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+ .start = IRQ_DB8500_PMU,
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+ .end = IRQ_DB8500_PMU,
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+ .flags = IORESOURCE_IRQ,
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+ },
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+};
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+
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+/*
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+ * The PMU IRQ lines of two cores are wired together into a single interrupt.
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+ * Bounce the interrupt to the other core if it's not ours.
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+ */
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+static irqreturn_t db8500_pmu_handler(int irq, void *dev, irq_handler_t handler)
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+{
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+ irqreturn_t ret = handler(irq, dev);
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+ int other = !smp_processor_id();
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+
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+ if (ret == IRQ_NONE && cpu_online(other))
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+ irq_set_affinity(irq, cpumask_of(other));
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+
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+ /*
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+ * We should be able to get away with the amount of IRQ_NONEs we give,
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+ * while still having the spurious IRQ detection code kick in if the
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+ * interrupt really starts hitting spuriously.
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+ */
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+ return ret;
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+}
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+
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+struct arm_pmu_platdata db8500_pmu_platdata = {
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+ .handle_irq = db8500_pmu_handler,
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+};
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+
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+static struct platform_device db8500_pmu_device = {
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+ .name = "arm-pmu",
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+ .id = -1,
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+ .num_resources = ARRAY_SIZE(db8500_pmu_resources),
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+ .resource = db8500_pmu_resources,
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+ .dev.platform_data = &db8500_pmu_platdata,
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+};
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+
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+static struct platform_device db8500_prcmu_device = {
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+ .name = "db8500-prcmu",
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+};
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+
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+static struct platform_device *platform_devs[] __initdata = {
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+ &u8500_dma40_device,
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+ &db8500_pmu_device,
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+ &db8500_prcmu_device,
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+};
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+
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+static resource_size_t __initdata db8500_gpio_base[] = {
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+ U8500_GPIOBANK0_BASE,
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+ U8500_GPIOBANK1_BASE,
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+ U8500_GPIOBANK2_BASE,
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+ U8500_GPIOBANK3_BASE,
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+ U8500_GPIOBANK4_BASE,
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+ U8500_GPIOBANK5_BASE,
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+ U8500_GPIOBANK6_BASE,
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+ U8500_GPIOBANK7_BASE,
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+ U8500_GPIOBANK8_BASE,
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+};
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+
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+static void __init db8500_add_gpios(struct device *parent)
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+{
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+ struct nmk_gpio_platform_data pdata = {
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+ .supports_sleepmode = true,
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+ };
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+
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+ dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base),
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+ IRQ_DB8500_GPIO0, &pdata);
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+ dbx500_add_pinctrl(parent, "pinctrl-db8500", U8500_PRCMU_BASE);
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+}
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+
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+static int usb_db8500_rx_dma_cfg[] = {
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+ DB8500_DMA_DEV38_USB_OTG_IEP_1_9,
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+ DB8500_DMA_DEV37_USB_OTG_IEP_2_10,
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+ DB8500_DMA_DEV36_USB_OTG_IEP_3_11,
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+ DB8500_DMA_DEV19_USB_OTG_IEP_4_12,
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+ DB8500_DMA_DEV18_USB_OTG_IEP_5_13,
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+ DB8500_DMA_DEV17_USB_OTG_IEP_6_14,
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+ DB8500_DMA_DEV16_USB_OTG_IEP_7_15,
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+ DB8500_DMA_DEV39_USB_OTG_IEP_8
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+};
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+
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+static int usb_db8500_tx_dma_cfg[] = {
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+ DB8500_DMA_DEV38_USB_OTG_OEP_1_9,
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