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+/*
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+ * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
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+ *
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+ * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
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+ *
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+ * This file is automatically generated from the AM33XX hardware databases.
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation version 2.
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+ *
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+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
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+ * kind, whether express or implied; without even the implied warranty
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+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <linux/i2c-omap.h>
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+
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+#include "omap_hwmod.h"
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+#include <linux/platform_data/gpio-omap.h>
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+#include <linux/platform_data/spi-omap2-mcspi.h>
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+
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+#include "omap_hwmod_common_data.h"
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+
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+#include "control.h"
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+#include "cm33xx.h"
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+#include "prm33xx.h"
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+#include "prm-regbits-33xx.h"
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+#include "i2c.h"
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+#include "mmc.h"
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+
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+/*
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+ * IP blocks
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+ */
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+
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+/*
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+ * 'emif_fw' class
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+ * instance(s): emif_fw
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+ */
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+static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
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+ .name = "emif_fw",
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+};
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+
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+/* emif_fw */
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+static struct omap_hwmod am33xx_emif_fw_hwmod = {
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+ .name = "emif_fw",
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+ .class = &am33xx_emif_fw_hwmod_class,
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+ .clkdm_name = "l4fw_clkdm",
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+ .main_clk = "l4fw_gclk",
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+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
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+ .modulemode = MODULEMODE_SWCTRL,
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+ },
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+ },
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+};
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+
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+/*
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+ * 'emif' class
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+ * instance(s): emif
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+ */
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+static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
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+ .rev_offs = 0x0000,
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+};
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+
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+static struct omap_hwmod_class am33xx_emif_hwmod_class = {
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+ .name = "emif",
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+ .sysc = &am33xx_emif_sysc,
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+};
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+
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+static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
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+ { .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, },
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+ { .irq = -1 },
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+};
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+
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+/* emif */
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+static struct omap_hwmod am33xx_emif_hwmod = {
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+ .name = "emif",
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+ .class = &am33xx_emif_hwmod_class,
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+ .clkdm_name = "l3_clkdm",
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+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
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+ .mpu_irqs = am33xx_emif_irqs,
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+ .main_clk = "dpll_ddr_m2_div2_ck",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
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+ .modulemode = MODULEMODE_SWCTRL,
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+ },
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+ },
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+};
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+
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+/*
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+ * 'l3' class
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+ * instance(s): l3_main, l3_s, l3_instr
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+ */
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+static struct omap_hwmod_class am33xx_l3_hwmod_class = {
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+ .name = "l3",
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+};
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+
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+/* l3_main (l3_fast) */
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+static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
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+ { .name = "l3debug", .irq = 9 + OMAP_INTC_START, },
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+ { .name = "l3appint", .irq = 10 + OMAP_INTC_START, },
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+ { .irq = -1 },
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+};
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+
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+static struct omap_hwmod am33xx_l3_main_hwmod = {
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+ .name = "l3_main",
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+ .class = &am33xx_l3_hwmod_class,
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+ .clkdm_name = "l3_clkdm",
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+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
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+ .mpu_irqs = am33xx_l3_main_irqs,
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+ .main_clk = "l3_gclk",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
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+ .modulemode = MODULEMODE_SWCTRL,
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+ },
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+ },
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+};
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+
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+/* l3_s */
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+static struct omap_hwmod am33xx_l3_s_hwmod = {
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