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@@ -89,3 +89,108 @@ static const unsigned int h2_keymap[] = {
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KEY(0, 5, KEY_F13),
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KEY(1, 5, KEY_F14),
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KEY(2, 5, KEY_F15),
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+ KEY(3, 5, KEY_F16),
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+ KEY(4, 5, KEY_SLEEP),
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+};
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+
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+static struct mtd_partition h2_nor_partitions[] = {
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+ /* bootloader (U-Boot, etc) in first sector */
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+ {
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+ .name = "bootloader",
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+ .offset = 0,
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+ .size = SZ_128K,
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+ .mask_flags = MTD_WRITEABLE, /* force read-only */
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+ },
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+ /* bootloader params in the next sector */
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+ {
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+ .name = "params",
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+ .offset = MTDPART_OFS_APPEND,
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+ .size = SZ_128K,
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+ .mask_flags = 0,
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+ },
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+ /* kernel */
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+ {
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+ .name = "kernel",
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+ .offset = MTDPART_OFS_APPEND,
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+ .size = SZ_2M,
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+ .mask_flags = 0
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+ },
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+ /* file system */
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+ {
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+ .name = "filesystem",
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+ .offset = MTDPART_OFS_APPEND,
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+ .size = MTDPART_SIZ_FULL,
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+ .mask_flags = 0
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+ }
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+};
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+
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+static struct physmap_flash_data h2_nor_data = {
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+ .width = 2,
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+ .set_vpp = omap1_set_vpp,
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+ .parts = h2_nor_partitions,
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+ .nr_parts = ARRAY_SIZE(h2_nor_partitions),
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+};
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+
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+static struct resource h2_nor_resource = {
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+ /* This is on CS3, wherever it's mapped */
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+ .flags = IORESOURCE_MEM,
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+};
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+
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+static struct platform_device h2_nor_device = {
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+ .name = "physmap-flash",
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+ .id = 0,
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+ .dev = {
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+ .platform_data = &h2_nor_data,
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+ },
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+ .num_resources = 1,
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+ .resource = &h2_nor_resource,
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+};
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+
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+static struct mtd_partition h2_nand_partitions[] = {
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+#if 0
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+ /* REVISIT: enable these partitions if you make NAND BOOT
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+ * work on your H2 (rev C or newer); published versions of
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+ * x-load only support P2 and H3.
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+ */
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+ {
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+ .name = "xloader",
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+ .offset = 0,
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+ .size = 64 * 1024,
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+ .mask_flags = MTD_WRITEABLE, /* force read-only */
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+ },
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+ {
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+ .name = "bootloader",
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+ .offset = MTDPART_OFS_APPEND,
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+ .size = 256 * 1024,
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+ .mask_flags = MTD_WRITEABLE, /* force read-only */
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+ },
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+ {
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+ .name = "params",
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+ .offset = MTDPART_OFS_APPEND,
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+ .size = 192 * 1024,
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+ },
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+ {
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+ .name = "kernel",
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+ .offset = MTDPART_OFS_APPEND,
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+ .size = 2 * SZ_1M,
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+ },
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+#endif
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+ {
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+ .name = "filesystem",
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+ .size = MTDPART_SIZ_FULL,
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+ .offset = MTDPART_OFS_APPEND,
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+ },
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+};
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+
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+#define H2_NAND_RB_GPIO_PIN 62
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+
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+static int h2_nand_dev_ready(struct mtd_info *mtd)
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+{
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+ return gpio_get_value(H2_NAND_RB_GPIO_PIN);
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+}
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+
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+static struct platform_nand_data h2_nand_platdata = {
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+ .chip = {
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+ .nr_chips = 1,
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+ .chip_offset = 0,
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+ .nr_partitions = ARRAY_SIZE(h2_nand_partitions),
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