|  | @@ -261,3 +261,32 @@
 | 
	
		
			
				|  |  |  /* Bit masks for USB_POWER */
 | 
	
		
			
				|  |  |  
 | 
	
		
			
				|  |  |  #define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
 | 
	
		
			
				|  |  | +#define          nENABLE_SUSPENDM  0x0       
 | 
	
		
			
				|  |  | +#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
 | 
	
		
			
				|  |  | +#define             nSUSPEND_MODE  0x0       
 | 
	
		
			
				|  |  | +#define               RESUME_MODE  0x4        /* DMA Mode */
 | 
	
		
			
				|  |  | +#define              nRESUME_MODE  0x0       
 | 
	
		
			
				|  |  | +#define                     RESET  0x8        /* Reset indicator */
 | 
	
		
			
				|  |  | +#define                    nRESET  0x0       
 | 
	
		
			
				|  |  | +#define                   HS_MODE  0x10       /* High Speed mode indicator */
 | 
	
		
			
				|  |  | +#define                  nHS_MODE  0x0       
 | 
	
		
			
				|  |  | +#define                 HS_ENABLE  0x20       /* high Speed Enable */
 | 
	
		
			
				|  |  | +#define                nHS_ENABLE  0x0       
 | 
	
		
			
				|  |  | +#define                 SOFT_CONN  0x40       /* Soft connect */
 | 
	
		
			
				|  |  | +#define                nSOFT_CONN  0x0       
 | 
	
		
			
				|  |  | +#define                ISO_UPDATE  0x80       /* Isochronous update */
 | 
	
		
			
				|  |  | +#define               nISO_UPDATE  0x0       
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* Bit masks for USB_INTRTX */
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
 | 
	
		
			
				|  |  | +#define                   nEP0_TX  0x0       
 | 
	
		
			
				|  |  | +#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
 | 
	
		
			
				|  |  | +#define                   nEP1_TX  0x0       
 | 
	
		
			
				|  |  | +#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
 | 
	
		
			
				|  |  | +#define                   nEP2_TX  0x0       
 | 
	
		
			
				|  |  | +#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
 | 
	
		
			
				|  |  | +#define                   nEP3_TX  0x0       
 | 
	
		
			
				|  |  | +#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
 | 
	
		
			
				|  |  | +#define                   nEP4_TX  0x0       
 | 
	
		
			
				|  |  | +#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
 |